This contribution aims at improving the performance of Dynamic Differential Cascode Voltage Switch Logic (Dy-DCVSL) and Enhanced Dynamic Differential Cascode Voltage Switch Logic (EDCVSL) and suggests three architectures for the same. The first architecture uses transmission gates (TG) to reduce the logic tree depth and width, which results in speed improvement. As leakage is a dominant issue in lower technology nodes, the second architecture is proposed by adapting the leakage control technique (LECTOR) in Dy-DCVSL and EDCVSL. The third proposed architecture combines features of both the first and the second architectures. The operation of the proposed architectures has been verified through extensive simulations with different CMOS submicron technology nodes (90 nm, 65 nm, and 45 nm). The delay of the gates based on the first architecture remains almost the same for different functionalities. It is also observed that Dy-DCVSL gates are 1.6 to 1.4 times faster than their conventional counterpart. The gates based on the second architecture show a maximum of 74.3% leakage power reduction. Also, it is observed that the percentage of reduction in leakage power increases with technology scaling. Lastly, the gates based on the third architecture achieve similar leakage power reduction values to the second one but are not able to exhibit the same speed advantage as achieved with the first architecture.
Digital design space is filled with a variety of logic styles suitable for different applications [
The paper is arranged in five sections including the present one. Section
Differential Cascode Voltage Switch Logic (DCVSL) is a differential style derived from conventional CMOS logic and ratioed pseudo NMOS logic. It combines their advantages and provides a high speed, area efficient, and rail-to-rail logic design alternative. Both the static and the dynamic versions of the DCVSL style are available in open literature. This section briefly describes existing dynamic DCVSL styles (Dy-DCVSL).
The generic architecture of a Dy-DCVSL gate is shown in Figure
(a) Generic architecture of Dy-DCVSL circuit: (b) two- and (c) three-input Dy-DCVSL XOR-XNOR gate.
Cross-coupled transistors M3 and M4 help output to switch and transistors M5 and M6 accelerate this process [
The generic architecture of the EDCVSL circuits is drawn in Figure
(a) Generic architecture of EDCVSL circuit: (b) two-input and (c) three-input EDCVSL XOR-XNOR gate.
This section presents three new architectures to improve performance of existing Dy-DCVSL and EDCVSL. The first architecture aims at speed improvement, the second works on leakage reduction, and the third combines features of the first two architectures to see their combined effect on performance.
Proposed architecture-1 is based on shifting the function realized by PDN logic tree to a separate block and using transmission gates (TG) logic for its implementation. The new Dy-DCVSL and EDCVSL circuits based on architecture-1 are named Dynamic TG based DCVSL (Dy-TG-DCVSL) and Dynamic TG based EDCVSL (TG-EDCVSL) circuits, respectively. A generic architecture of Dy-TG-DCVSL circuit along with two- and three-input XOR-XNOR realization is depicted in Figure
(a) Proposed architecture-1 for Dy-TG-DCVSL circuits. (b) Two-input and (c) three-input Dy-TG-DCVSL XOR-XNOR gate.
The working of the proposed Dy-TG-DCVSL XOR2 gate can be explained for the two phases. The operation in precharge phase is the same as conventional Dy-DCVSL. Any changes in the inputs A and B may update the gate potential of M9 and M10 but will not affect the output, since M8 is OFF. Consequently, when CLK becomes high, the output gets evaluated according to the gate potential of M9 and M10. In comparison to the conventional Dy-DCVSL XOR-XNOR gate (Figure
(a) Proposed architecture-1 for TG-EDCVSL circuits. (b) Two-input and (c) three-input TG-EDCVSL XOR-XNOR gates.
The differential nature of the DCVSL logic style has several advantages but in submicron regions it needs attention. For all input combinations, one of the two logic tree branches in the PDN will be conducting while the other would remain nonconducting. The nonconducting branch in submicron regions would have some amount of current due to OFF transistors in the path in both precharge and evaluation phases. This current can be classified as leakage current. To improve the performance in submicron region, these currents need to be minimized. Various leakage reduction techniques based on the use of sleep transistor [
Proposed architecture-2 for (a) Dy-DCVSL-LCT circuits and (b) EDCVSL-LCT circuits.
To understand the leakage control mechanism in Dy-DCVSL-LCT and EDCVSL-LCT circuits, the operating regions of LCTs during precharge and evaluation phases are examined. In the precharge phase, both the OUT and the OUTB are at
Proposed architecture-3 combines the features of proposed architecture-1 and proposed architecture-2. The resulting Dy-DCVSL and EDCVSL structures are called Dy-TG-DCVSL-LCT and TG-EDCVSL-LCT. The proposed architectures are shown in Figure
Proposed architecture-3 based (a) Dy-TG-DCVSL-LCT and (b) TG-EDCVSL-LCT circuits.
This section presents the simulation results for the new Dy-DCVSL circuits based on the proposed architectures. The simulations are performed using Symica tool and the PTM technology parameters for 90 nm, 65 nm, and 45 nm nodes. The frequencies of the inputs CLK, A, B, and C are 50 MHz, 25 MHz, 12.5 MHz, and 6.25 MHz, respectively. FO4 of inverters is maintained as the load in all the gates. The results are categorized into three sections according to the proposed architectures. The leakage power is computed on the basis of leakage current and the power supply.
Dy-TG-DCVSL and TG-EDCVSL based two-input AND-NAND (AND-NAND2), three-input AND-NAND (AND-NAND3), two-input exclusive-OR (XOR-XNOR2), and three-input exclusive-OR (XOR-XNOR3) circuits are simulated using 90 nm CMOS technology parameters. The simulation waveforms of the Dy-TG-DCVSL and TG-EDCVSL XOR-XNOR2 and XOR-XNOR3 gates are shown in Figure
Simulation waveform of Dy-TG-DCVSL and TG-EDCVSL based (a) two-input XOR-XNOR gate and (b) three-input XOR-XNOR gate.
The gates are also designed in Dy-DCVSL and EDCVSL styles to analyze the speed advantage. The corresponding delay results are noted and enlisted in Table
Summary of delay results (ps).
Gate | Style | |||
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Dy-DCVSL | EDCVSL | Dy-TG-DCVSL | TG-EDCVSL | |
AND-NAND2 | 500 | 480 | 350 | 340 |
AND-NAND3 | 570 | 530 | 355 | 345 |
XOR-XNOR2 | 500 | 480 | 350 | 341 |
XOR-XNOR3 | 550 | 490 | 355 | 345 |
In this category, the leakage current reduction through incorporation of LECTOR technique in dynamic DCVSL circuits is demonstrated. An XOR-XNOR2 gate is chosen as the test bench due to its wide range of applications. The conventional Dy-DCVSL, EDCVSL, Dy-DCVSL-LCT, and EDCVSL-LCT XOR-XNOR2 gate circuits are simulated at various submicron technology nodes such as 90 nm, 65 nm, and 45 nm. Table
Leakage power (nW) for the conventional Dy-DCVSL, EDCVSL-LCT and PA-2 Dy-DCVSL-LCT, EDCVSL-LCT based XOR-XNOR2 gate topologies.
Inputs | Architecture | ||||||
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Conventional | PA-2 | Reduction with respect to conventional (%) | |||||
A | B | Dy-DCVSL | EDCVSL | Dy-DCVSL-LCT | EDCVSL-LCT | Dy-DCVSL-LCT | EDCVSL-LCT |
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0 | 0 | 9.27 | 8.9 | 4.02 | 4.06 | 56.6 | 54 |
0 | 1 | 0.23 | 0.21 | 0.16 | 0.14 | 30.4 | 33 |
1 | 0 | 0.23 | 0.21 | 0.16 | 0.14 | 30.4 | 33 |
1 | 1 | 9.27 | 8.9 | 4.02 | 4.06 | 56.6 | 54 |
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0 | 0 | 12.9 | 12.88 | 5.16 | 5 | 60 | 61 |
0 | 1 | 0.41 | 0.27 | 0.27 | 0.18 | 32.2 | 33.3 |
1 | 0 | 0.41 | 0.27 | 0.27 | 0.18 | 32.2 | 33.3 |
1 | 1 | 12.9 | 12.88 | 5.16 | 5 | 60 | 61 |
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0 | 0 | 22.48 | 22.48 | 5.79 | 5.79 | 74 | 74.3 |
0 | 1 | 0.41 | 0.28 | 0.28 | 0.18 | 33.8 | 35.7 |
1 | 0 | 0.41 | 0.28 | 0.28 | 0.18 | 33.8 | 35.7 |
1 | 1 | 22.48 | 22.48 | 5.79 | 5.79 | 74 | 74.3 |
The following observations are made from Table The percentage reduction ranges in the leakage power are 30.4%–56.6% for 90 nm, 32.2%–61% for 65 nm, and 33.8%–74.3% for 45 nm. Leakage power tends to follow an increasing trend with the scaling down of the technology. An increase in percentage reduction is seen as we dig down the lower technology nodes.
Dy-TG-DCVSL, TG-EDCVSL, Dy-TG-DCVSL-LCT, and TG-EDCVSL-LCT two-input XOR2 and three-input XOR3 gates are simulated at various technology nodes. Out of the two dynamic styles, the results pertaining to EDCVSL circuits are listed in Tables A percentage reduction range of 27%–64% for 90 nm, 30%–66% for 65 nm, and 38%–76% for 45 nm in leakage power is observed. The TG-EDCVSL-LCT XOR-XNOR2 gate shows less leakage power with respect to Dy-TG-DCVSL counterpart. Leakage power tends to follow an increasing trend with the scaling down of the technology. The percentage reduction in the leakage power increases with the lower technology nodes. The delay of the TG-EDCVSL-LCT XOR-XNOR2 gate is more than the Dy-TG-DCVSL due to the presence of the high resistance path for leakage current reduction, thus exhibiting a trade-off between the speed and leakage power reduction.
Leakage power (nW) for TG-EDCVSL and TG-EDCVSL-LCT based XOR-XNOR2 gate topologies.
Inputs | Architecture | |||
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A | B | TG-EDCVSL | TG-EDCVSL-LCT | Reduction with respect to TG-EDCVSL (%) |
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0 | 0 | 8.8 | 4 | 55 |
0 | 1 | 0.18 | 0.13 | 27 |
1 | 0 | 0.18 | 0.13 | 27 |
1 | 1 | 8.8 | 4 | 55 |
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0 | 0 | 12.7 | 5 | 61 |
0 | 1 | 0.2 | 0.14 | 30 |
1 | 0 | 0.2 | 0.14 | 30 |
1 | 1 | 12.7 | 5 | 61 |
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0 | 0 | 22.24 | 5.7 | 74.3 |
0 | 1 | 0.21 | 0.13 | 38 |
1 | 0 | 0.21 | 0.13 | 38 |
1 | 1 | 22.24 | 5.7 | 74.3 |
Leakage power (nW) in TG-EDCVSL and TG-EDCVSL-LCT three-input XOR-XNOR gates.
Inputs | Architecture | ||||
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A | B | C | TG-EDCVSL | TG-EDCVSL-LCT | Reduction with respect to TG-EDCVSL (%) |
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0 | 0 | 0 | 9.8 | 4 | 59 |
0 | 0 | 1 | 0.34 | 0.21 | 64 |
0 | 1 | 0 | 0.34 | 0.21 | 64 |
0 | 1 | 1 | 9.8 | 4 | 59 |
1 | 0 | 0 | 0.34 | 0.21 | 64 |
1 | 0 | 1 | 9.8 | 4 | 59 |
1 | 1 | 0 | 9.8 | 4 | 59 |
1 | 1 | 1 | 0.34 | 0.21 | 64 |
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0 | 0 | 0 | 14 | 5.07 | 63 |
0 | 0 | 1 | 0.38 | 0.26 | 66 |
0 | 1 | 0 | 14 | 5.07 | 63 |
0 | 1 | 1 | 0.38 | 0.26 | 66 |
1 | 0 | 0 | 0.38 | 0.26 | 66 |
1 | 0 | 1 | 14 | 5.07 | 63 |
1 | 1 | 0 | 14 | 5.07 | 63 |
1 | 1 | 1 | 0.38 | 0.26 | 66 |
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0 | 0 | 0 | 24.5 | 5.85 | 76 |
0 | 0 | 1 | 0.43 | 0.12 | 72 |
0 | 1 | 0 | 0.43 | 0.12 | 72 |
0 | 1 | 1 | 24.5 | 5.85 | 76 |
1 | 0 | 0 | 0.43 | 0.12 | 72 |
1 | 0 | 1 | 24.5 | 5.85 | 76 |
1 | 1 | 0 | 24.5 | 5.85 | 76 |
1 | 1 | 1 | 0.43 | 0.12 | 72 |
Delay measurement for the PA-1 based and the PA-3 based ED-CVSL XOR/XNOR gate.
Mode of operation | A | B | Output | Delay |
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PA-1 based XOR gate | ||||
Evaluation | 1 | 1 | 1->0 | 300 ps |
0 | 0 | 1->0 | 299 ps | |
Precharge | 1 | 1 | 0->1 | 184 ps |
0 | 0 | 0->1 | 187 ps | |
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PA-3 based XOR gate | ||||
Evaluation | 1 | 1 | 1->0 | 355 ps |
0 | 0 | 1->0 | 354 ps | |
Precharge | 1 | 1 | 0->1 | 598 ps |
0 | 0 | 0->1 | 598 ps |
In this paper, three new architectures to enhance the performance of Dy-DCVSL and EDCVSL are proposed. The first improves the speed by using transmission gates through logic tree depth reduction. The second architecture is derived to reduce leakage power at lower technology nodes. The incorporation of leakage control by incorporating LECTOR technique is proposed. The third architecture merges the two proposed architectural modifications to analyze their combined effect on the performance. Extensive simulations are done at various CNOS submicron technology nodes such as 90 nm, 65 nm, and 45 nm. It is observed that dynamic DCVSL gates based on the first architecture are 1.6 to 1.4 times faster than the conventional dynamic CVSL circuits. The gates based on the first architecture show almost equal delay values irrespective of the implemented functionality. A maximum leakage power reduction of 78.43% is achieved with the second architecture based DCVSL gates. An increasing trend in the leakage power with the scaling down of the technology is observed in the proposed circuits. Lastly, the third architecture achieves the same leakage power reduction values as the second one but is not able to exhibit the same speed advantage as achieved with the first architecture.
The authors declare that there are no conflicts of interest regarding the publication of this paper.