Optimal Design of Voltage Reference Circuit and Ring Oscillator Circuit Using Multiobjective Differential Evolution Algorithm

Tis paper deals with the optimal design of diferent VLSI circuits, namely, the CMOS voltage reference circuit and the CMOS ring oscillator (RO). Te optimization technique used here is the multiobjective diferential evolution algorithm (MDEA). All the circuits are designed for 90nm technology. Te main objective of the CMOS voltage reference circuit is to minimize the voltage variation at the output. Te targeted value of the reference voltage is 550 mV. A CMOS ring oscillator (RO) is designed depending on the performance parameters such as power consumption and phase noise. Te optimal transistor sizing of each circuit is obtained from MDEA. Each circuit is implemented in SPICE by taking the optimal dimensions of the transistors, and the performance parameters are achieved. Te designed voltage reference circuit achieves a reference voltage of 550mV with 600nW power dissipation. Te reference voltage variation of 8.18% is observed due to temperature variation from − 40 ° C to+125 ° C. Te MDEA-based optimal design of RO oscillates at 2.001GHz frequency, has a phase noise of − 87dBc/Hz at 1MHz ofset frequency, and consumes 71 μ W power. Tis work mainly aims to optimize the MOS transistors’ sizes using MDEA for better circuit performance parameters. SPICE simulation has been carried out by using the optimal values of MOS transistor sizes to exhibit the performance parameters of the circuit. Simulation results establish that design specifcations are closely met. SPICE results show that MDEA is a better technique for the optimal design of the above-mentioned VLSI circuits.


Introduction
Circuit sizing is a tedious problem for the IC engineer.Evolutionary techniques are efcient in solving circuit sizing problems.J. H. Holland invented the genetic algorithm (GA) [1].GA is utilized for op-amp design in [2].With the help of GA, power dissipation is optimized for an active load differential amplifer [3].GA-based VLSI circuit partitioning is reported in [4].Te foorplan area is optimized using GA in [5].A CMOS circuit synthesizer called DARWIN [6] is proposed for op-amp design.Particle swarm optimization (PSO) [7,8] is a profcient evolutionary method.PSO-based design of op-amp is reported in [9,10].PSO is applied for the optimal design of current conveyors [11].Storn and Price introduced diferential evolution (DE) [12].DE is used for analog circuit synthesis in [13].DE-based channel routing for the VLSI circuit is proposed in [14].DE is useful for VLSI foorplanning [15].A hybrid particle swarm optimization (PSO) method is proposed for the optimization of an operational amplifer [16] and a diferential amplifer [17].In [18], a rule-guided genetic algorithm (RG-GA) is employed to design an operational amplifer.A machine learning-assisted sizing technique [19] is introduced to design amplifers and a comparator in analog circuits.Bayesian optimization approaches have been reported for analog circuit sizing in [20,21].Deep reinforcement learning [22] is utilized for sizing a two-stage operational amplifer.Various evolutionary optimization techniques [23][24][25][26][27][28] are applied to the circuit sizing of other analog VLSI circuits.Many optimization problems exhibit a multiobjective nature, and evolutionary approaches prove to be benefcial for solving such problems.In 2003, Babu and Jehan introduced the multiobjective diferential evolutionary algorithm (MDEA) [29].Te multiobjective DE [30] is employed to address the power dispatch problem, and the PID controller tuning using a multiobjective DE is discussed in [31].Several studies on multiobjective numerical optimization have been documented in [32][33][34][35].A CMOS voltage reference circuit is proposed in [36,37], and a nine-stage ring oscillator circuit is designed in [38,39].Te paper's contribution is the application of a state-ofthe-art algorithm for the optimal design of a voltage reference circuit and a ring oscillator circuit.Tis article aims to optimize the transistor's dimensions for each circuit for better performance parameters.Te paper is written as follows: the optimization problem for each circuit is formulated in Section 2. MDEA is described in the next section.In Section 4, the simulation results are explained.Section 5 concludes the article.

Optimization Problem Formulation
Te CMOS voltage reference circuit is shown in Figure 1, and the nine-stage ring oscillator circuit is shown in Figure 2. MDEA is utilized for the optimal design of these two circuits.

Design of a CMOS Voltage Reference Circuit.
For MOSFET, the drain current I D at the subthreshold region is described as where K � W/L, μ denotes the carrier mobility, C ox denotes the oxide capacitance/area, V T denotes the thermal voltage, V TH represents the threshold voltage for MOSFET, and η denotes the subthreshold slope factor.For large values of V D , I D is not dependent on V DS and is represented by V GS1 in M 1 equals the sum of V GS2 in M 2 and V DSR1 in M R1 . ( Te current fowing through transistors M 1 and M 2 is equal to I P .Te value of V DSR1 is given by Te resistance of the MOS transistor M R1 is given by Te current I P is represented as Te current fowing through M 4 and M 6 is 3I P and 2I P , respectively.Te output reference voltage V REF is represented as V TH and V T have negative and positive TC, respectively; the V REF can be obtained with zero TC by setting the transistor's dimensions.
Te design problem is formulated as follows: (1) Preserve the dimension of current mirror transistors where V max and V min denote the absolute maximum and minimum of the diference between V REF and V Target within the temperature range −40 °C to 125 °C.(6) Te cost function (CF) is formulated as where η varies between 0.7 and 0.9, N denotes the number of CMOS inverter stages, I r (t f ) denotes the rise (fall) time, I D is the drain current, C tot represents the total capacitance, and V DD represents the supply.Te total capacitance C tot is given by where L n (L p ) denotes the length of NMOS (PMOS) and W n (W p ) represents width of the NMOS (PMOS).Te average power dissipation [40] of the RO is represented as Te phase noise [40] is defned as where V char � ΔδV/c, δf is the ofset frequency, δV denotes the gate over drive voltage, T represents the absolute temperature, and k denotes the Boltzmann constant, c � 2/3 Te fgure of merit (FOM) is given as Te optimization problem can be represented as follows: (1) minimization of L{δf}, (2) minimization of the power, and (3) minimize FOM.
Te design constraints are given as follows: Te MDEA is applied to get the design parameters for the RO.Journal of Electrical and Computer Engineering

Multiobjective Differential Evolutionary Algorithm (MDEA)
Te multiobjective diferential evolution (MODE) algorithm [29][30][31] is a specialized variant of the diferential evolution (DE) algorithm developed to tackle multiobjective optimization problems.By integrating the principles of diferential evolution and Pareto dominance, MODE enables the exploration of trade-of solutions that balance conficting objectives.Te following are the key steps involved in the MODE algorithm: (1) Initialization: An initial population of candidate solutions is generated randomly within the search space.Te MODE algorithm employs a population-based evolutionary search strategy to explore the solution space and discover diverse solutions that represent trade-ofs among multiple objectives.Its objective is to approximate the Pareto-optimal front, which comprises the set of nondominated solutions.Te algorithmic steps are described as follows: (see Algorithm 1).
Apply the naïve and slow approach [32] to eliminate the dominant solutions from the previous generation.
Output the nondominated solutions.

Simulation Results and Discussions
Te MDEA technique is executed in MATLAB for the analog VLSI circuits depicted in Figures 1 and 2, respectively.
x i,j,g otherwise. } Determine whether the target vector survives for the next generation.

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Journal of Electrical and Computer Engineering MDEA.Cadence is used to simulate the circuits for authentication purposes.A discussion of the results is given below.

Simulation Results for the CMOS Voltage Reference
Circuit.Te constraints for the frst circuit are given as 2 V, VREF � 550 mV, and IP � 100 nA.Table 2 shows the optimal transistor sizing obtained from MDEA.Te voltage reference circuit is implemented with these design parameters in Cadence Virtuoso.Te variation of VREF with the temperature is displayed in Figure 3 at diferent process corners such as TT, SF, FS, FF, and SS.Te deviation of VREF from the target value of 0.55 V is less than 10% across diferent process corners.Te variation of VREF with respect to temperature and supply voltage for the TT process is shown in Figure 4.It is observed that the reference voltage varies from 0.53 V to 0.6 V for the TT process.Te variation of VREF with respect to temperature and supply voltage for the SS process is shown in Figure 5.It is observed that the reference voltage varies from 0.54 V to 0.61 V for the SS process.Te variation of VREF with respect to temperature and supply voltage for the FF process is shown in Figure 6.It is observed that the reference voltage varies from 0.52 V to 0.59 V for the FF process.Te variation of VREF with respect to temperature and supply voltage for the SF process is shown in Figure 7.It is observed that the reference voltage varies from 0.53 V to 0.61 V for the SF process.Te variation of VREF with respect to temperature and supply voltage for the FS process is shown in Figure 8.It is observed that the reference voltage varies from 0.53 V to 0.59 V for the FS process.Te temperature is varied from −40 °C to 125 °C, the supply voltage is from 1 V to 1.4 V for all the processes, and the maximum variation of the reference voltage from the target value is less than 12.2%.Table 3 demonstrates the diferent performance parameters of the voltage reference circuit.Te power dissipation of the voltage reference circuit is 600 nW.It is evident from Figures 4-8 and Table 3 that the voltage reference circuit is very robust for variation against temperature, supply voltage, and diferent process corners.MDEA shows better results as compared to SCA-mGWO [30].

Simulation Results for the CMOS Ring Oscillator Circuit.
Table 4 presents the constraints and optimal design parameters obtained through the application of the multiobjective diferential evolutionary algorithm (MDEA).Te ring oscillator (RO) circuit is designed using Cadence Virtuoso with the gpdk090 library.Te transient response of the RO is illustrated in Figure 9, showcasing oscillation at a frequency of 2.001 GHz. Figure 10 displays the phase noise plot for the designed RO circuit, revealing a phase noise of −87 dBc/Hz at 1 MHz.Te power dissipation plot for the RO circuit is shown in Figure 11, with the optimized circuit dissipating a power of 71 μW.Te achieved fgure of merit

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Journal of Electrical and Computer Engineering (FOM) for this design is −164.487dBc/Hz.In [38], a nine-stage RO circuit was also investigated, operating at a frequency of 2.13 GHz.At this frequency, the power dissipation was reported as 477.7 μW, and the phase noise was measured as −91.4 dBc/Hz at 1 MHz.Te reported FOM in [38] was −16118 dBc/Hz.Comparatively, the MDEA-based design of the RO circuit demonstrates superior performance parameters, as summarized in Table 5.

Conclusion
In this study, the multiobjective diferential evolutionary algorithm (MDEA) is employed to achieve optimal designs for CMOS VLSI circuits.By efciently identifying the optimal design parameters for both circuits, the MDEA enables the reconstruction of each circuit within the Cadence environment.Te voltage reference circuit successfully achieves a reference voltage of 550 mV, meeting the targeted specifcations.However, it is worth noting that a variation of 8.18% in the reference voltage is observed due to temperature fuctuations ranging from −40 °C to + 125 °C.Te designed ring oscillator (RO) circuit exhibits stable oscillation at a frequency of 2.001 GHz, accompanied by a phase noise of −87 dBc/Hz at an ofset frequency of 1 MHz.Additionally, the power consumption of the RO circuit is measured at 71 μW.Notably, the SPICE simulation results demonstrate that the MDEA-based circuit design fulflls all the required performance parameters.Furthermore, the outcomes obtained through the MDEA approach surpass those reported in previous literature.Tus, the MDEA algorithm proves its efcacy in designing optimal RO and voltage reference circuits.

MC 1 ,
MC 2 and M 1 , M 2 .(2) Preserve the dimension of transistors MC 3 , MC 4 , and MC 5 for matching purpose.(3) Te current through MC 3 , MC 4 , and MC 5 must be greater than the leakage currents, i.e., 1 nA.(4) Preserve the dimension of transistors M 3 , M 4 , M 5 , M 6 , and M 7 for matching purpose.(5) Te optimization problem aims to reduce the variation for the V REF within the temperature range from −40 °C to 125 °C.Te variation of V REF with temperature is represented as

( 2 )
Mutation: Each individual in the population undergoes mutation, where a mutant solution is created by perturbing the individual using a mutation operator.Te mutation operator typically involves the diference between multiple individuals.(3) Crossover: Te mutant solutions are combined with the original individuals to produce trial solutions.Te crossover process merges the components of the mutant and original solutions.(4) Selection: Te trial solutions are evaluated, and individuals are selected for the next generation based on Pareto dominance.Te selection process compares solutions, determining their superiority or noninferiority relative to others in the population.Dominated solutions are eliminated, while nondominated solutions are retained.(5) Termination: Steps 2 to 4 are repeated until a termination criterion is met.Tis criterion may involve a maximum number of generations, the attainment of a specifc convergence level, or other predefned stopping conditions.

Figure 3 :
Figure 3: Variation of V REF for diferent corners.

Figure 4 :
Figure 4: Variation of V REF with temperature and V DD for TT process.

Figure 5 :
Figure 5: Variation of V REF with temperature and V DD for SS process.

Figure 6 :
Figure 6: Variation of V REF with temperature and V DD for FF process.

Figure 8 :
Figure 8: Variation of V REF with temperature and V DD for FS process.

Figure 7 : 1 Figure 10 :
Figure 7: Variation of V REF with temperature and V DD for SF process.

Figure 9 :
Figure 9: Transient response of the RO.

Table 1
displays the parameters of MDEA.Te optimal transistor dimensions for each circuit are obtained fromStep 1: Initialize D (dimension of optimization problem), N p (population size), F (scaling factor), CR (crossover rate), and g max (Maximum iteration cycle) Step 2:Initialize for g � 0 the D-dimensional N p populations as x → i,g � x 1,i,g , x 2,i,g , ..., x D,i,g   (where i � 1, 2,..., N P ) within the bounds x → min � x 1, min , ..., x D, min

Table 2 :
Transistor sizing of the voltage reference circuit.

Table 3 :
Comparison of design performance parameters for the voltage reference circuit.

Table 4 :
MDEA-based optimal design parameters for RO circuit.