Comprehensive Analysis of ZVS Operation Range and Deadband Conditions of a Dual H -Bridge Bidirectional DC-DC Converter with Phase Shift Control

. Tis study ofers a thorough examination of the zero voltage switching (ZVS) operation range and deadband conditions for a bidirectional DC-DC converter with phase shift control, featuring dual H-bridge. Te analysis considers the soft switching range of the DAB converter, accounting for the impact of the headband and the ZVS capacitor. By applying the diferential equation of the circuit during deadband time, a sufcient constraint for the input and output bridges can be calculated. Te fndings indicate that as the output voltage increases, the minimum phase shift value required to achieve ZVS decreases, and expanding the phase shift value will expand the ZVS range and reduce switching losses. Te study provides simulation results for various operating conditions, validating the theoretical analysis of the proposed system. In addition, the results furnish information about the circuit behavior during the deadband and waveforms. Finally, MATLAB/SIMULINK verifes the simulation results for diferent operating stages.


Introduction
Te double-active-bridge (DAB) converters are highly advantageous compared to other bidirectional-isolated topologies due to their small size, low cost, ease of implementation, and ability to achieve zero-voltageswitching (ZVS) [1][2][3][4][5].As a result, they have been widely adopted in applications requiring bidirectional power transmission.Previous research on isolated bidirectional DC/DC converters has primarily focused on topology, control strategies, and modeling approaches using classical control theory [6][7][8].Te literature proposes dual-phaseshift (DPS) control [9] to eliminate reactive power, reduce peak current, and power loss in the DAB converter and determine the on/of state of a simple semiconductor.However, this proposal does not examine the ZVS operating range, which is dependent on factors such as voltage conversion ratios and phase change ratios.Te loss of ZVS not only reduces efciency but also causes electromagnetic interference (EMI) issues [10][11][12].
Te authors of [13] introduced a new hybrid switching modulation approach for an isolated bidirectional DC-DC converter used in a DC microgrid energy storage system.Tis method combines pulse width modulation and hysteresis current control techniques to achieve zero-voltage switching (ZVS) and improved stability under diferent operating conditions.Nevertheless, this control strategy has some disadvantages, such as circulating current and backfow power in the voltage-fed dual-active-bridge converter during heavy load conditions, as highlighted in [14].
In the study of [15], a phase-shifted modulation (PSM) method was introduced to minimize current ripple in a modular multilevel converter of a bidirectional DC-DC converter, even under unstable operating conditions.Tis method involves adjusting the phase-shift angle between the pulse width modulation (PWM) signals of the half-bridge cells of the modular multilevel converter.Although efective in reducing current ripple, this PSM method is computationally complex due to its optimization problem formulation.In addition, determining the optimal phase-shift angle requires solving a convex optimization problem, which can be time-consuming [16][17][18].Despite the efectiveness of various modulation schemes in achieving ZVS over wide load ranges, it remains challenging to achieve full ZVS capability over the entire load range due to the high implementation complexity [19].
Te proposed bidirectional DC-DC converter circuit topology is depicted in Figure 1.Te converter can operate in two modes, depending on the power fow direction.Te converter comprises two H-bridge structured converters, referred to as bridges one and two, which are isolated by a 5 kHz high-frequency transformer.Te frst H-bridge has four IGBT-diode switches [S 11 -S 14 ], with two seriesconnected IGBTs per leg, and a snubber capacitor connected to each of the IGBTs to achieve zero voltage switching and minimize turn-of overvoltage.Te second H-bridge operates at low voltage and is confgured with four IGBTdiode switches [S 21 -S 24 ], connected to a small snubber capacitor to minimize switching loss [20,21].
Te converter is bidirectional, and each H-bridge can be primary or secondary depending on the power fow direction.Te circuit operates in buck mode when power fows from the high voltage side (HVS) to the low voltage side (LVS) and in boost mode when the power fow is reversed.A deadband is inserted between the interlocked switches in the same bridge to prevent shooting through during commutation, ensuring the reliability of highvoltage and high-power converters [22][23][24][25][26][27][28][29][30][31].However, the deadband may cause waveform distortion and other unexpected transient processes, as depicted in Figure 2.During the deadband, all switches in the same H-bridge module are turned of, including the four switches [S 11 -S 14 ] on the primary side [24].
Tis research presents a straightforward theoretical analysis of the steady-state power conditions, the impact of the ZVS capacitor and the deadband on the soft switching operation range of the DAB converter, with varying objectives such as enhancing the ZVS operation range or improving efciency.Te adequate constraints for input and output bridges for soft switching are determined by resolving the diferential equation of the circuit during the deadband.
Te article is structured as follows.Section 2 provides the operating principle of the proposed DAB bidirectional DC/ DC converter.In Section 3, power fow analysis is introduced.Section 4 examines the full-bridge ZVS condition, while Section 5 discusses the converter's behavior during the dead time.Section 6 provides simulation results for the above method.Finally, Section 7 presents the conclusions drawn from the study.

Operating Principle of the Proposed a DAB
Bidirectional DC/DC Converter  2.
L s is the sum of transformer leakage inductance and auxiliary inductors.ZVS operation was achieved by connecting snubber capacitors parallel to switches.ZVS can be achieved in both leading and full lagging bridges when V ab and V cd change their sign from negative to positive.

Principle Operation.
Based on the on/of state of the switches, there are diferent operation modes.Figure 3 illustrates the six segments that emerge during each switching cycle.Te following assumptions are made in order to simplify the analysis process: (1) Te summation of the transformer leakage inductance and the auxiliary inductor current increases from a negative value at the beginning of the switching cycle to a positive value at the end of the half-switching period (2) Te converter is operating at a steady state where V cd ′ is the transformer's secondary voltage generated by the bridge 2, referred primary voltage  4 Terefore, the voltage of the ZVS capacitor of S 22 during the deadtime zone can be expressed as follows: where  3(D)).During this mode, the i Ls are at their maximum.
where V ds11 (t) and V ds12 (t) are the voltages across C 11 , and C 12 , respectively, during this stage, and V ds12 (t) can be obtained.
i Ls (t 3 ) Taking into account that the initial values of V ds12 (0) � − V ab and i dc11 (0) � i dc11 (t 4 ).From equations ( 6) and ( 7), the following equations can be formulated: Equation ( 8) can be simplifed further to where Te voltage of the ZVS capacitor and the inductance current i Ls in this stage is plotted in Figure 5 i Ls is the inductance current fowing through the snubber capacitors on the primary side and can be expressed as follows: During this short time, the voltage V ds12 and V ds13 will decrease, and the Snubber capacitors C 12 and C 13 are still being discharged by snubber capacitors C 11 and C 14 , while V ab is negatively increasing from zero.Similarly, when t � t 5 the ZVS capacitors of S 11 and S 14 are fully charged, and the ZVS capacitors of S 12 and S 13 are discharged [24].
As a result, the body diodes D 12 and D 13 become conductive, setting up conditions for S 12 and S 13 to be turned on with ZVS in the following stage.Te ZVS capacitor voltage of S 11 can be expressed using equations ( 6), (7), and (10). where In Figure 6, several variations of V ds11 (t) are plotted versus values of the ZVS capacitor at V HB � 270V, V LB � 28V and L s � 460μH according to the dead time during this stage.Te maximum value of V ds11 decreases as the capacitor size increases.As a result, V ds11 has a lower peak value than V HB when C ds � 0.45nF and C ds � 0.5nF.For the ZVS to operate correctly, the peak capacitor voltage must be obtained during the deadband [6].

Stage 5 [t 5 , t 6 ].
At the beginning, S 12 and S 13 are ON, and S 11 and S 14 are OFF.Transformer leakage inductance and auxiliary inductors fow into the load through D 21 and D 24 , while primary current fows through D 12 and D 13 .At t � t 6 , the secondary side current decreases from positive to zero.Tere is zero voltage turn-on for active switches, and no turn-on loss exists (see Figure 3(F)).

Stage 6 [t 6 , t 7
].At t � t 6 , switches S 12 and S 13 are still on, while switches S 11 and S 14 are of.Charges on C 12 and C 13 will discharge through S 12 and S 13 .Te primary current will fow through S 12 , S 13 , while the negative current of the transformer leakage inductance will fow through S 21 and S 24 .Terefore, S 21 and S 24 will be turned of at t � t 6 (see Figure 3(G)).
During this period, No switching occurs at t 6 .It is a short time interval only to illustrate the conversion of current fow from the D 12 andD 13 mode to the S 12 and S 13 mode.Terefore, the current will discharge the snubber capacitors of C 12 and C 13 and charge C 11 and C 14 .
Figure 7 depicts the circuit operation when one leg of bridge one consisting of S 11 and S 12 operates with zero voltage switching (ZVS).As shown in Figure 2, the current is positive before the deadband time and fows into S 11 , as seen Providing a gating signal at the point when D 12 is conducting enables S 12 to turn on with ZVS, as shown in Figure 7(d), as the current in D 12 decreases to zero and alternates its polarity.
Te circuit modes when S 11 and S 12 operate at ZVS are depicted in Figure 8.During this time interval, prior to the turn-on of S 11 , the current is negative, as shown in Figure 2, and the switching voltages are illustrated in Figure 8(a).Deadband time initiates once S 11 is turned of.As seen in Figure 8(b), the current fowing in commutates to the snubber capacitors, where C 11 discharges from VHB to zero, and C 12 charges from zero to VHB.Once the charging and

Power Flow Analysis
Te power transfer can be controlled by adjusting the phase shift between the transformer's primary voltage V ab and secondary voltage V cd [32].In buck mode, power fows from Bridge 1 to Bridge 2 at a voltage conversion ratio of k < 1. Te polarity of the V ab and V cd changes from negative to positive as shown in Figure 2. Tus, under steady-state conditions, the average value of the DC current at the bridge 2 i cd2 must be zero.Based on fgure t 2 � DT sh , t 4 � T sh , t 7 � (1 + D)T sh , k � V ab /nV cd and f s � 1/(2T sh ).Te expression of the inductance current can be obtained.Table 3 summarizes the inductor current steady-state expressions for forwarding power fow directions.
Moreover, i Ls (t 0 ) � − i Ls (t 4 ) and i Ls (t 2 ) � − i Ls (t 7 ).From the above condition, we can express i Ls at time t 0 , t 2 , t 4 , and t 7 as follows: Terefore, the average input current can be expressed as Consequently, the transmission power controlled by SPS can be expressed as a function of the feeding voltage as follows: Te equation (16) indicates that the powers are directly proportional to the phase shift ratio of the two bridges D. By employing a single-phase shift control, one can represent the normalized transmission power in the following manner: where P max is the maximum power of the converter.Terefore, Referring to Figure 2, the maximum inductor current (I max � i Ls (t 4 )) can be expressed as When the converter operates at full load and the minimum value of the input, while the input current has a maximum value, therefore, under these conditions, the current stress can be determined as follows: Equation (20) shows that the current stress of the converter is a function of the maximum phase shift, the maximum value of the voltage ratio, and the value of leakage inductance in the SPS control mode.
Figure 9 shows the output power as a function of the phase shift angle.Te maximum power is achieved at a phase shift angle of (π/2), as evident from the graph, indicating that equation ( 16) has reached its maximum and zero transmission power points.In addition, increasing the phase shift ratio results in higher transmission power values.During power transmission in the forward direction, the source-side bridge leads to the load-side bridge, while in reverse mode, the loading side bridge leads to the source side bridge.Figure 9(d) depicts the relationship between current stress and phase shift at diferent voltage conversion ratios in SPS control under full load.Te graph indicates that, with a constant shift ratio D, current stress decreases as the voltage conversion ratio k is reduced.Terefore, it is recommended to decrease the voltage conversion and phase shift ratio as much as possible to minimize the converter's current stress, reduce losses, and improve efciency [24,27].

Full Bridge ZVS Condition
4.1.Zero Voltage Switching Limits.According to the abovegiven transition analysis, to ensure full ZVS operation, the inductor current should be negative at (t 0 ) and positive at t 2 and t 4 .In order to achieve ZVS in both leading and lagging full bridges, i Ls (t 2 ) and i Ls (t 4 ) must be greater than zero.However, to realize ZVS at t � t 0 , the leakage inductance energy should be greater than the amount of energy required to charge and discharge the output capacitors in the leading bridge.Terefore, the leakage inductance current can be written as follows: 8 Journal of Electrical and Computer Engineering

Intervals
Inductor current Journal of Electrical and Computer Engineering 9 Due to the symmetry of the leakage inductance current i Ls (t 0 ) � − i Ls (t 2 ), equation ( 19) describes the maximum inductor current.As i Ls (0) ≤ 0, by equation ( 21), we can write the equation as follows: where k � (V LB /nV HB ) is the voltage conversion between the output voltage on the primary side of the converter and the input voltage, equation (22) shows that when k ≥ 1, there is a requirement of D to realize ZVS of the leading bridge.
Regarding the lagging leg bridge, to achieve ZVS operation (power transfer from the high voltage side to the low voltage side), the current of the leakage inductance must be positive.
Since i Ls (DT sh ) ≥ 0, equation ( 23) can be presented in the following form: Te normalized load resistance R L can be obtained as In equation (24), i cd2 represents output current and D is required to achieve ZVS of the lagging bridge when k ≤ 1.Furthermore, when k ≥ 1, the lagging bridge is usually achieved, which is the limiting condition for ZVS.Whenever k � 1, ZVS is fulflled for any value of D. Te above analysis can be summarized in Table 4.
Figure 10(a) displays the Zero Voltage Switching (ZVS) region of the DAB converters based on equations ( 22) and (24), where the phase shift is represented on the x-axis, and the relationship between the output and input voltages is shown on the y-axis.Te bold curves indicate the operating zone of the DAB converter under ZVS conditions.When k � 1, complete control of ZVS is achievable.However, under light load conditions where k ≠ 1, the ZVS region diminishes.Te operational phase shift is determined by the intersection of the k line and the load line R L .Increasing the phase shift leads to a larger ZVS region and lower switching loss but higher reactive current value and conduction loss, while decreasing the phase shift produces the opposite efect.To expand the operating range of ZVS, it is necessary to select the maximum feasible values for L seq and D max .Te theoretical maximum D value is 0.5, but the output power's nonlinearity is more severe for a value of D close to 0.5 because the output power's evolution with D is parabolic [9].Terefore, the maximum value of the phase shift and leakage inductance is determined by the maximum transmission power as follows: A phase shift and the power at which ZVS is lost in the converter can be estimated using the following equations:

Required Dead times.
As mentioned in the transition above, the leakage inductance current must be sufcient to complete the charging and discharging of the capacitor.To achieve ZVS, the dead time must be longer than the voltage capacitor connected in parallel across the switch discharging from the DC input voltage to zero V.As a result, the resonance occurs.During stage 4 [t 4 , t 5 ], the voltage across C 12 and C 13 decreases to zero and is completely discharged at t � t 5 , D 12 and D 13 are conducive naturally.Moreover, the voltage of S 12 and S 13 is also clamped to zero, and ZVS is achieved when switches S 12 and S 13 are turned on at this time.In order to ensure that S 12 and S 13 will turn ON with ZVS, a dead time is necessary between the turn-of of S 11 and S 14 and the turn-on of S 12 and S 13 .To ensure that D 12 and D 13 are conducting before turning ON S 12 and S 13 should be larger than the time of discharging C 12 and C 13 .Accordingly, the dead-time t dead can be described as follows: After the leakage inductance current i Ls discharges C 12 , C 13 completely, the body diodes D 12 , D 13 will be conductive, resulting in an increase in voltage across V ds11 and V ds14

Mode of operation
equal to the input DC voltage V HB .According to equation ( 11), the following equation can be derived: Based on Figure 2, the leakage inductance current must be greater than zero during the whole dead band [t 4 , t 5 ].Tis condition can be expressed as follows: According to (22), condition (30) can be presented in the following form: Furthermore, the minimum value of the current i Lsmin is required to achieve zero voltage switching at t � t 5 , ensuring that the voltage across S 11 and S 14 reaches and equal to the input DC voltage V HB .Consequently, the inductance current i Ls decreases linearly, as shown in Figure 2. Hence, at t � t 4 , the i Ls � i Ls (t 4 ); V ds11 and V ds14 � 0, V ds12 and V ds13 � V HB .Terefore, at t � t 5 , V ds11 and V ds14 � V HB ; V ds12 and V ds13 � 0, and i Ls � i Lsmin .Te magnitude of i dc1 (t 4 ) should be greater than i Lsmin so that the inductance current will fully charge the snubber capacitors C 11 and C 14 while the voltage across S 11 and S 14 reaches the input DC voltage V HB .Terefore, we say: W tran represents the amount of energy transferred, assuming no loss occurs at the circuit.ZVS operates under the condition that V HB � DV ds during this stage, therefore Te following expression can be obtained by comparing ( 32) and ( 33): Te magnitude of i dc1 (t 4 ) should be greater than i Lsmin in order to ensure that the inductance current fully charges the snubber capacitors C 11 and C 14 while the voltage across S 11 and S 14 reaches the input DC voltage V HB .Due to this, If equation ( 29) is not satisfed, the i dc1 (t 2 ) amount is smaller than i dc1min .As a result, the C 11 and C 14 are not charged up to V HB , while the C 12 and C 13 are not discharged to zero.Terefore, the zero voltage switching operation cannot be achieved.Te efciency will decrease as a result of switching loss.Accordingly, the voltage of S 12 can be expressed as follows: Tus,

Input Bridge Boundary
Output Bridge Boundary 0 0.5

ZVS Zone
Hard Switching Input Bridge Zone where t is the time after the dead time started.At the end of the dead time t � t 5 , V ds12 (t 5 ) is not zero because i Ls (t 4 ) < i Lsmin .C 12 is shorted out and discharges rapidly from V ds12 (t 5 ) to zero.C 11 suddenly charges from V HB − V ds12 (t 5 ) to V HB .During dead time, the S 11 voltage must reach V HB to ensure S 12 will turn on with ZVS.Accordingly, Formulas ( 10) and ( 13), as well as (36) and (38), can be used to determine sufcient restrictions for input bridge ZVS operation: Formula (39) guarantees that the amount of L s is suffcient to fully charge the zero-voltage switching capacitor of switch S 11 .Conversely, during the deadband, formula (40) ensures that V ds11 across S 11 reaches the input DC voltage V HB .As a result, the minimum value of the deadband zone or the maximum value of the ZVS capacitor can be limited [31].
A sufcient constraints output bridge requires the voltage V ds22 across S 22 to reach the output DC voltage V LB during the headband.Consequently,

Behaviour of Converter during the Deadtime
Figure 11 illustrates a simulation of the switching waveforms during the operational states.When the time reaches t � t 0 , the HV bridge enters its deadtime phase, causing the AC inductor current to fow from the active switches to the opposite antiparallel diode pair.Tis leads to the primary Hbridge being ahead of the secondary H-bridge, resulting in no phase shift error being detected [33,34].As a consequence, when the dead time commences at t � t 1 , the output voltage of the LV bridge remains unchanged in polarity.Te AC inductor current fowing in the anti-parallel diode of the LV bridge prevents the switching transition from altering the transmission path.
Since the phase shift error (D db ) is caused by the current that slews during the deadtime period, an expression that describes the slew time (D s ) can be derived [33].Also, since the AC inductor current is cyclic and half-wave symmetric, the positive peak current and the negative peak current have the same magnitude (|i(t 0 )| � |i(t 4 )|).Tis means that by setting (i(t 4 ) � − i(t 0 )), a method for deriving this expression is presented in [34], an expression for D s can be solved for both the leading and lagging switching alternatives as where D c represents the commanded phase shift, and D DT is the deadtime period in radians.From the slew time equation (42), the phase shift error D db is determined by frst identifying the converter operating condition.Tis is necessary because the phase shift error augments the applied phase shift when the HV bridge leads the LV bridge and reduces it when the HV bridge lags the LV bridge.Tis allows D db to be determined based on D s .Te relationship between D s and D db is therefore summarized in Table 5.

Simulation Results
MATLAB Simulink was used to simulate the circuit schematic shown in Figure 1 in order to verify the previous theoretical considerations.Table 6 contains the specifcations and parameters of the system.Te simulation outcomes for the gating signals and steady-state operation waveforms in the buck mode at 5 kW rated power and a high-frequency transformer are demonstrated in Figure 12, which is consistent with the waveform simulated in Figure 2. Te primary voltage of the transformer, the output voltage of the secondary bridge, the 12 Journal of Electrical and Computer Engineering voltage across an inductor, and the inductor current all exhibit the same attributes as the fundamental operating waveform of the bidirectional forward converter depicted in Figure 2. Figure 13(a) shows waveforms of the gate signals G 1 and G 2 applied to S 11 and S 12 , V ds11 and V ds12 are the voltages across S 11 and S 12 , respectively, and i Ls .It can be seen that the currents i Ls > 0 and i Ls < 0 during the turn-on instants of S 12 and S 11 , respectively.Te zoomed views of S 12 and S 11 when turned On are shown in Figures 13(b) and 13(c), respectively.Te S 11 starts to turn OFF at t � τ α .For t ≤ τ α , V ds11 and V ds12 are zero and 270 V, respectively (see Figure 13(c)).It can be observed that after t � τ α , V ds12 decreases until it equals zero, while V ds11 increases linearly to 270 V.When t � τ α1 , the S 12 will turn on.In addition, before t � τ α1 , V ds12 � 0, and i Ls is positive at t � τ α1 .Terefore, D 12 conducts from t � τ α1 to t � τ α2 .Te switch S 12 conducts from t > τ α2 as i Ls become negative.It can be seen from Figure 13(c) that V ds12 � 0 at t � τ α1 , indicating the ZVS turnon conduction of S 12 .Similarly, as can be seen from Figure 13(b), i Ls become positive concerning t > τ β1 , so after t � τ β2 , S 11 begins to conduct at zero voltage V ds1 � 0.     Similarly, you can predict the ZVS operation of the bridge-2 converter.Figure 14 depicts a comparison between the simulation results of this study and a previous one [8], in terms of the minimum phase shift needed for the input and output bridges to meet the necessary and sufcient constraints for various output voltages.Te graph demonstrates that for the lagging bridge, the minimum phase shift required to achieve ZVS decreases as the output voltage increases.On the other hand, for the leading bridge, as the output voltage increases, the minimum phase shift required to achieve ZVS increases.As a result, increasing the phase shift can widen the ZVS range and reduce switching losses, but it can also increase reactive current and conduction losses.Conversely, reducing the phase shift can lead to the opposite results.Terefore, to achieve a successful design, it is crucial to evaluate the tradeof between these factors.
Te boundaries for zero voltage switching (ZVS) are presented in Figure 15, where the power handled by the converter is depicted on the x-axis.By selecting a value of K that is marginally above 1, the operating range of the converter with ZVS can be substantially expanded.
Table 7 shows the comparison simulation results of the value of the phase shift and the power at which ZVS is lost in the leading and lagging bridge between this paper and compared reference paper [8] for diferent values of the output voltage.Using the value of k equal to 1, the ZVS operation will be lost approximately at 0, 400 and 750 W  when the sufcient boundaries to operate with D ZVS are 0, 0.0167, and 0.02, respectively, for the leading bridge (input bridge).While the ZVS operation will be lost approximately for the lagging bridge at 3200, 2150, and 1250 W, when the sufcient boundaries to operate with D ZVS are 0.054, 0.049, and 0.025, respectively, for the reference paper [8] (see Figures 14(a) and 15(a) and Table 6).Furthermore, as can also be seen from the Figures 14(b) and 15(b) and Table 6, ZVS operation will be lost approximately at 100, 400, and 1000 W when D ZVS are 0.0125, 0.016, and 0.04 for the leading bridge.While the ZVS operation will be lost approximately for the lagging bridge at 1700, 740, and 250 W, when the sufcient boundaries to operate with D ZVS are 0.0125, 0.016, and 0.04, respectively.Moreover, the operating range using ZVS can greatly increase when the k value is slightly larger than one.
When the phase shift of a dual active H-bridge bidirectional DC-DC converter is increased, the duration of overlap between upper and lower switches is reduced, leading to a decrease in switching losses.However, increasing the phase shift also causes an increase in conduction losses and reactive current, as the switching devices are subjected to higher voltage stress, resulting in increased conduction losses.In addition, the increase in reactive current results in losses from the converter's reactive components.Tis can cause a decrease in the efciency of the converter.Figure 16 illustrates power efciency curves that vary with load variation, and the efciency is signifcantly low under light load conditions due to ZVS being under the RMS phase current.Te RMS currents through the switches determine conduction losses.Under heavy load conditions, the converter is highly efcient because the circulating current decreases, resulting in low conduction losses.

Conclusions
Tis article presents a detailed theoretical analysis of the steady-state power conditions, the impact of the ZVS capacitor, and the deadband on the soft switching operation range of the DAB converter with phase shift control.Te simulation results are in agreement with the theoretical analysis.Te adequate conditions for achieving ZVS are calculated for both the input and output bridges, and the boundaries of sufcient conditions for ZVS operation are plotted.A comparison of sufcient constraints between our proposed system and previous studies is provided, indicating that our proposed restrictions are more accurate.Te study shows that as the output voltage increases, the minimum phase shift value required to achieve ZVS decreases.Increasing the value of D expands the ZVS range and reduces switching losses, as noted in [9].

Figure 1 :
Figure 1: Te DAB DC-DC converter: (a) proposed circuit schematic diagram and (b) the equivalent circuit.

Figure 3 :
Figure 3: (a) Commutation step diagrams during a switching cycle in power fow; (b) equivalent circuits of SPS controlled converter for forwarding operation.

4
Journal of Electrical and Computer Engineering where

Figure 4 :
Figure 4: Te voltage of the ZVS capacitor and the inductance current i Ls : (a) charging the snubber capacitors of S 22 , S 23 , (b) discharging the snubber capacitors of S 21 and S 24 , and (c) increasing the inductance current.

Figure 5 :
Figure 5: Te voltage of the ZVS capacitor and the inductance current i Ls (a) charging the snubber capacitors of S 11 , S 14 , (b) discharging the snubber capacitors of S 12 , S 13 , and (c) decreasing the inductance current.

Figure 9 :Figure 8 :
Figure 9: (a) Dependency of the output power on operating phase shift and leakage inductance for DAB converter.(b) A dependency of the output power on operating phase shift frequency for DAB converter.(c) Output power characterization A versus phase shift ratio of the DAB.(d) Efect of phase shit ratio on the current stress under full load condition.

Figure 10 (
Figure 10(b) plots the phase shift and ZVS boundaries of the input and output bridges against the voltage gain ratio for diferent values of the ZVS capacitor.It can be observed that as the ZVS capacitor increases, the ZVS region decreases.To expand the operating range of ZVS, it is necessary to select the maximum feasible values for L seq and D max .Te theoretical maximum D value is 0.5, but the output power's nonlinearity is more severe for a value of D close to 0.5 because the output power's evolution with D is parabolic[9].Terefore, the maximum value of the phase shift and leakage inductance is determined by the maximum transmission power as follows:

Figure 10 :
Figure 10: (a) ZVS zone in leading and lagging DAB converter, R L is load resistance; (b) phase shift and ZVS boundaries under the diferent value of voltage gain ratio.

Figure 11 :
Figure 11: Deadtime efect-the primary H-bridge leads the secondary H-bridge.

Figure 13 :
Figure 13: Impact of dead time on the primary bridge and ZVS turn-on operation of the switches S 11 and S 12 of the DAB.

Figure 14 :
Figure14:A simulation comparison of the necessary and sufcient constraints to achieve ZVS for input and output bridge under diferent output voltage between this paper and[8] using D as the x-axis.From top to bottom, V LB � 20 V, 28 V, and 35 V, respectively.(a) Paper[8]; (b) this paper.

Figure 15 :
Figure15: Sufcient constraints to achieve ZVS for input and output bridge under diferent output voltage between this paper and[8] using the power as the x-axis.From top to bottom, V LB � 20 V, 28 V, and 35 V, respectively.(a) Paper[8]; (b) this paper.
Te dual active bridge bidirectional converter uses a singlephase-shift control method to regulate power fow between two DC sources, as shown in Figure2.Te primary H-bridge switches (S 11 and S 14 ) and secondary H-bridge switches (S 21 -S 24 ) have identical gate signals, with complementary signals for S 11 and S 12 having a 50% duty cycle.Tis generates a voltage (±V ab ) on the primary side of the transformer.Similarly, a voltage (±V cd ) is generated on the secondary side by controlling the switches on the secondary bridge with the same signals as the primary bridge, but with an appropriate phase shift to achieve bidirectional power transfer.Te primary voltage is represented by V ab , and the phase shift between the two bridges is denoted by DT hs .Te switching frequency is f s , and T hs is half the switching period, T 2.1.Te Topology of the Proposed Circuit and Control Strategy.hs � 1/2f s .Te current i Ls is the sum of the transformer leakage inductance and the auxiliary inductors of the secondary bridge.Te equations for a half-cycle are sufcient, given the current waveform's half-wave symmetry in Figure 2.2.1.Stage 0 [t 0 , t 1 ].S 11 and S 14 of the frst bridge are turned on at this stage.V ab is a positive voltage.Te value of i Ls is increasing from a negative to a positive value.S 11 and S 14 were turned of, and the current fow through the body diodes D 11 and D 14 .Due to this, S 22 and S 23 switches will operate under ZVS conditions; the secondary current fows through the body diodes D 2 and D 3 , while the current will charge the snubber capacitors C 21 and C 24 .Te stage will end 2Journal of Electrical and Computer Engineering when the i Ls current reaches zero (see Figure3(A)).During this mode, the total dynamic current is i Ls (t) � i Ls t 0  + At t � t 2 , switches S 22 and S 23 are turned of due to the snubber capacitors C 22 and C 23 , and the dead time stage begins.Secondary currents charge and discharge Snubber capacitors of S 22 , S 23 , and S 21 , S 24 , respectively.V cd is the voltage across the capacitor, which gets positive from zero.Te voltage of the ZVS capacitor and the inductance current i Ls in this stage is plotted in Figure 2.2.2.Stage 1 [t 1 − t 2 ].Switches S 11 and S 14 are still in the On state, and current fows through them.Te current will charge the snubber capacitors of C 12 and C 13 and discharge the capacitors of C 11 and C 14 .Consequently, the initial voltages of C 12 and C 13 are VHB, and those of C 11 , and C 14 , are zero.On the secondary side, switches S 22 and S 23 are still on, i Ls is greater than 0, and current fows through switches S 22 and S 23 (see Figure 3(B)).2.2.3.Stage 2 [t 2 − t 3 ].

21 and S 24 to turn on under ZVS conditions. When charging and discharging have been completed to the point where the voltages of C 21 and C 24 become zero, while the voltages of C 22 and C 23 become V cd , current fows through D 21 and D 24 diodes (see Figure 3(C)). Te switches S 21 and S 24 are turned
ds22 is the voltage across C 22 , z 2 is the resonant impedance, C ds is the zero-voltage switch capacitor, and ω 2 is the self-oscillating frequency.Te voltage across C 22 and C 23 will increase as the voltage across C 21 and C 24 continues to decrease, allowing S , t 4 ].At t � t 3 , the second bridge's switch S 21 and S 24 , will be turned on.Due to i Ls > 0, the secondary current will fow through the body diodes D 21 and D 24 , which will discharge the capacitors C 21 and C 24 .Te primary bridges S 11 and S 14 remain turned on, and current fows through S 11 and S 14 (see Figure

Table 1 :
Te switches and output capacitance statuses.

Table 2 :
Te switches and output capacitance statuses.
while C 12 discharges from VHB to zero.Once C 12 's discharge process is complete, the current freewheels through D 12 .
Journal of Electrical and Computer Engineering discharging are complete, the current freewheels through commutates to the diode D 11 , where it is negative, as shown in Figure8(c).As turn-on gate signals are provided to S 11 , it begins to conduct at zero voltage once the current alternates its polarity, as illustrated in Figure8(d).Similarly, ZVS can be employed for visualizing other switches.

Table 3 :
Inductor current expression during diferent intervals.

Table 4 :
Te constraint of ZVS for the leading and lagging bridge.

Table 5 :
Te relationship between D s and D DT , and the phase shift error efect.

Table 6 :
Main proposed circuit parameters.
Simulation of the DAB for the proposed circuit: from top to bottom: gating signal for bridge one switches, gating signal for bridge two switches, circuit waveforms of V ab , V cd , and V Ls , respectively, and inductor current i Ls .

Table 7 :
[8]parison of the simulation results of this paper and reference paper[8].
18Journal of Electrical and Computer Engineering