Long Channel Carbon Nanotube as an Alternative to Nanoscale Silicon Channels in Scaled MOSFETs

Long channel carbon nanotube transistor (CNT) can be used to overcome the high electric field effects in nanoscale length silicon channel. When maximum electric field is reduced, the gate of a field-effect transistor (FET) is able to gain control of the channel at varying drain bias. The device performance of a zigzag CNTFET with the same unit area as a nanoscale silicon metaloxide semiconductor field-effect transistor (MOSFET) channel is assessed qualitatively. The drain characteristic of CNTFET and MOSFET device models as well as fabricated CNTFET device are explored over a wide range of drain and gate biases. The results obtained show that long channel nanotubes can significantly reduce the drain-induced barrier lowering (DIBL) effects in silicon MOSFET while sustaining the same unit area at higher current density.


Introduction
Carbon nanotubes (CNTs) are gaining momentum in the current silicon technology as a complementary nanostructure that could reform the device architecture.CNT modeling has been rigorously studied and examined [1][2][3][4][5] to assess the performance of the device at the circuit level.Advancement of the nanotechnology devices modeling is vital for the foreseeable future of carbon nanotube as switching device, interconnect and memory in integrated circuits (ICs).An in situ growth single-walled carbon nanotube (SWCNT), which integrates long channel 600 nm CNT channel, thin Al 2 O 3 top gate contact, and Palladium (Pd) metal source/drain contacts, has been demonstrated [6].
In addition, we report the potential of long channel 65 nm CNT as substitute to 45 nm silicon metal-oxide semiconductor field-effect transistor (Si MOSFET) from the perspective of modeling for future CNT-logic applications.We observe good agreement between CNTFET and Si MOSFET respectively, when simulating two-terminal drain currentvoltage (  -  ) characteristic.The projection has shed light on the reduction of DIBL and high field effects [7] as well as reduction in long channel CNT which is a widespread phenomenon in nanoscale Si MOSFET [8,9].We also demonstrate the effects of the channel area restructuring on the maximum electric field as well as density of states (DOS) in the conductance of CNT.Unlike MOSFET, it is revealed that the performance of CNT is enhanced when the source and drain width is minimized rather than the length, primarily due to the gate-to-source-drain parasitic fringe capacitances [10].MOSFET scaling in accordance with Moore's Law will reach its fundamental limitation as a result of process controllability in the next 10 years.Consequently, it is necessary to ensure that novel material is studied to provide alternatives to the current technologies and challenges in the new era of nanotechnology.

Carbon Nanotube and MOSFET Modeling
The layout of a CNTFET device is depicted in Figure 1.The area of the channel is given by the multiplication of the width, , of the source and drain contact and the length, , of the nanotube [6].Details of the quasiballistic MOSFET device modeling can be found in previous work in [11,12].
The carbon nanotube model [13] is a unified nanostructure model based on quantum transport theory established by Datta [14].This work extended the universal DOS spectral function [15] into the numerical calculation for CNT conduction subbands.We have included multiband density of states to account for multimode transport [16].For an accurate simulation, the input parameters shown in Table 1 for MOS-FET and CNTFET are extracted from TSMC [17] and Javey et al. [18], respectively.The 60 nm nanotube device model incorporate quasiballistic transport scattering as confirmed by [18].At 60 nm length, the carriers travelling on the CNT surface have smaller mean free path than acoustic phonon which occurred at 300 nm.
The typical width of a high-tech CNTFET device is reported [10] to be 1 m.The width of the CNT is calculated to be  CNT =  MOS / C , when both CNT and MOSFET devices are having identical channel area ( MOS =  CNT ).In a case when both devices can provide same level of current, channel area becomes  = () 2 when given the scaling factor;  and both parameter  = .CNT channel with length, 2  CNT , can provide the same current with  CNT = 0.5  CNT .Even when the physical widths of the CNT channel,  ≤ 0.5  CNT , there is no area drawback provided  ≥ 2  CNT .As nanotube channel length increases, maximum electric field in CNT,  CNT reduces tremendously [19,20].As for CNT with  = 60 nm, the maximum electric field is found to be   = (3/4) Si .
In the   -  simulation of CNTFET, Landauer-Buttiker formalism is utilized [21].The drain current,   is given as where  ON is the ON-conductance,  sc is the channel potential,   is the Fermi energy,   is the Boltzmann Constant,  is the temperature,  is the charge of an electron,   is the gate voltage,   is the drain voltage, and   is the source voltage.
The quantum conductance limit of a ballistic SWCNT is  ON = 4 2 /ℎ.The theoretical framework of (1) derivation can be found in [19,20].The quasi-one-dimensional (Q1D) density of state function of CNT [22] is given by where  cc = 1.42 Å and  = 3 eV is the carbon-to-carbon (C-C) bonding energy,   is the bandgap energy,   is the spin degeneracy, and  V is the valley degeneracy.On the other hand, the   -  characteristics for a short channel MOSFET can be expressed as where   is the gate capacitance,  ℓ is the gate-field dependent mobility,   sat is the saturation voltage at the point of current saturation,   is the critical voltage, and   is the threshold voltage.At current saturation, (3) becomes where  = V  /V sat is ratio of drift velocity, V  with saturation velocity and V sat at the drain [11,23].

Results and Discussion
Figure 2 shows the density of states for Q1D of [20,0] zigzag CNT with three van Hove singularities.As the energy span widens, more electrons are capable of occupying the singularities pinned between source and drain Fermi levels.
In the   -  simulation, the source Fermi energy is set to be at 0.22 eV below the conduction band.Our simulation results in Figure 3 which comes from (1) indicate that the CNT is able to offer drain current performance comparable to a 45 nm Si MOSFET.Remarkably, the effective current per  unit dimension yielded 53.5 times more of Si channel because of the small diameter tube.
The DIBL effects is suppressed fairly well for both devices with a slight advantage to CNT.Silicon demonstrated a superior subthreshold swing at 32.37 mV/dec, a value half of CNT.Although CNT has a lower on current, it sustains a high on-off ratio in 4 orders of magnitude.In addition to the device simulation, a SWCNT with a channel length of 600 nm is fabricated and shown in Figure 4.The Paladium contacts are made by electron beam lithography on SWCNT grown by thermal CVD from catalyst islands.The   -  measurement was carried out on a back gate geometry ≈200 nm SiO 2 depicted in Figure 5. From Figure 3, the gate characteristic,   -  , can be generated for the 60 nm CNT model and it is illustrated in Figure 6.The DIBL for the experimental data is at 1453 mV/V, while SS is estimated to be 664 mV/dec.Nevertheless, the 600 nm fabricated CNT is compensated by a high off-on ratio at 3.2 × 10 4 .It is found that DIBL can be lowered by at least one order of magnitude by doping the source end region of the channel [24] or the whole CNT [25,26].

Conclusion
It is revealed that long channel CNT can deliver drain current comparable to a MOSFET.The carrier density along the CNTFET is at least 50 times that of the Si MOSFET.In the same channel area, CNT has better control of short channel effect (SCE) than Si as it has lower   .This brings an enormous advantage since lower   has a smaller DIBL.A double gate or a cylindrical gate structure has the best control to suppress DIBL [27].Based on this, we could have lower offcurrent in the transistor.As a result, a CNT uses less power consumption as a switching device when operating at the same frequency as a MOSFET.

Figure 1 :
Figure 1: The unit area size of CNT channel with source and drain.

Figure 3 :
Figure 3: Drain characteristic of 60 nm single-walled carbon nanotube (colour solid lines) and 45 nm MOSFET (diamonds) with 0.1 V gate increment.Initial   for MOSFET is 0.4 V (bottom).

Figure 4 :
Figure 4: Plan view of SWCNT formed between Palladium source and drain contact.

Figure 5 :
Figure 5: Gate characteristics measurement of a 600 nm CNT from   = 0.05 to   = 1.0 V.

Table 1 :
Device model input and output parameter at   = 1 V.