Investigation of Low-Frequency Noise Characterization of 28-nm High-k pMOSFET with Embedded SiGe Source / Drain

We have studied the low-frequency noise characterizations in 28-nm high-k (HK) pMOSFET with embedded SiGe source/drain (S/D) through 1/f noise and random telegraph noise measurements simultaneously. It is found that uniaxial compressive strain really existed in HK pMOSFETwith embedded SiGe S/D.The compressive strain induced the decrease in the tunneling attenuation length reflecting in the oxide trap depth from Si/SiO 2 interface to the HK layer, so that the oxide traps at a distance from insulator/semiconductor interface cannot capture carrier in the channel. Consequently, lower 1/f noise level inHKpMOSFETwith embedded SiGe S/D is observed, thanks to the less carrier fluctuations from trapping/detrapping behaviors. This result represents an intrinsic benefit of HK pMOSFET using embedded SiGe S/D in low-frequency noise characteristics.


Introduction
Low-frequency noise is an important issue for analog, digital, mixed signal, and RF application.Nowadays, complementary metal-oxide-semiconductor (CMOS) technology has intruded into RF and/or analog circuits, and hence the excessive low-frequency noise will lead to a limitation of the functionality for related circuits [1,2].Low-frequency noise, including flicker (1/) noise and random telegraph noise (RTN), is increasingly attracting much interest in the CMOS device and technology community.In metal-oxidesemiconductor field-effect transistor (MOSFET) devices, the origin of 1/ noise and RTN is considered stemming from the carrier behaviors related to the oxide traps.1/ noise is most often due to fluctuations in carrier number and/or carrier scattering [3,4].RTN is another special kind of noise, which also appears in a low-frequency spectrum and originates from the trapping/detrapping behavior of a single or few traps [5,6].
On the other hand, the continued shrinking of conventional CMOS to enhance device performance has revealed limitations.The mobility enhancement has emerged as a key technology for improving drive current [7].Ways of optimizing channel mobility had been proposed to overcome the limitations on the scaling down of devices and to further improve the speed of CMOS circuits.The introduction of channel strain engineering in the state-of-the-art CMOS technology is recognized as an indispensable performance booster in producing next generation CMOS devices [8,9].For p-type MOSFET (pMOSFET), using embedded SiGe in the recessed source/drain (S/D) region can efficiently provide uniaxial compressive strain in the channel and improve hole mobility, bringing the enhancement of device performance [10][11][12].In addition, high-k (HK) materials are also adopted into advanced CMOS process for solving the increased gate leakage current.This is because HK dielectrics are the promising candidate for gate insulator to achieve low equivalent oxide thickness as required for the advanced CMOS technology nodes [13].However, a fabricated pMOSFET with SiGe S/D is possibly accompanied by the extra amount of process-induced defects, and a gate insulator that is replaced from conventional SiO 2 to HK materials usually causes the changes of trap properties in MOSFET, resulting in the influence on low-frequency noise characterizations.Though low-frequency noise characterizations in pMOSFET with SiGe S/D had been reported [12,14], low-frequency noise in HK pMOSFET with SiGe S/D is still unclear and needs to be addressed to improve the understanding.In this study, the low-frequency noise characterizations of HK pMOSFET with embedded SiGe S/D are investigated through 1/ noise and RTN measurements simultaneously.

Experimental
Apart from the S/D engineering, a 28-nm HK first/meta gate last technology was used to prepare the pMOSFET samples for this work.The thickness of the SiO 2 interfacial layer was approximately 1.0∼1.1 nm.A total of 20 atomic layer deposition cycles for HfO 2 were deposited on the top of the SiO 2 interfacial layer, and the thickness of all gate stacks was approximately 1.6∼1.7 nm.A thin TiN layer was deposited on HfO 2 layer as a capping layer for selective removal of the dummy poly-Si gate [15].After the S/D activation is annealed, the dummy poly-Si gate was removed and then other metals were deposited to tune the work function and achieve the idea value (5.0∼5.2) [16].The strained-Si HK pMOSFET structure features improvement by optimizing S/D recess shape following an epitaxially grown B-doped SiGe film embedded in the S/D regions with about 30% Ge concentration.Finally, the devices were completed with standard backend processes.The HK device without embedded SiGe was also fabricated and called as control device for comparison.The values of oxide capacitance derived from the equivalent oxide thickness of the CVC program [17] are 2.801 × 10 −6 and 2.746 × 10 −6 F/cm 2 for the control and the SiGe S/D devices, respectively.All the pMOSFETs with the gate dimension of 0.25 m × 0.04 m (width × length) were used in this work.Prior to low-frequency noise measurements, the dc characteristics were measured using an Agilent B1500 semiconductor parameter analyzer.The 1/noise measurements were carried out using SR570 lownoise current preamplifiers and an Agilent 35670A dynamic signal analyzer.The pMOSFETs were biased in linear operation (  = −50mV) while varying the gate overdrive voltage (  −   ) from the subthreshold regime (0.2 V) to the inversion regime (−0.3 V).The RTN measurements were made by waveform generator/fast measurement unit modules based on Agilent B1500 semiconductor parameter analyzer.

Results and Discussion
Figure 1 shows the drain current (  ) as a function of the drain voltage (  ) for both pMOSFETs.Around 18%   enhancement for SiGe S/D device is observed as compared to the control device at the same,   −   = −0.8V and   = −1.0V, which clearly indicates that the embedded SiGe S/D process can efficiently induce compressive strain in the channel.Figure 2 presents the drain current noise spectral density ( ID ) versus the frequency for both pMOSFETs taken from the average of six devices biased at different   −   .Both devices show typical 1/  noise types with the frequency exponent () close to unity.It means that the fluctuations of 1/ noise can be attributed to the carrier-number, mobility, or source-drain series-resistance fluctuations.In our devices, the  ID was found to be independent of the   , indicating that the 1/ noise source is not due to the contact or sourcedrain series resistance.The normalized drain current noise spectral density (LS ID / 2  ) and the transconductance to the drain current squared ((  /  ) 2 ) as functions of the   are plotted in Figure 3.The LS ID / 2  curves of both devices show fairly good proportionality with (  /  ) 2 at the low   level, indicating that the carrier number fluctuation dominates the 1/noise, which caused by trapping and releasing of the carrier in the gate stacks [4,5].However, the LS ID / 2  curves cannot follow this trend at the high   level, which implies a correlated mobility fluctuation was involved [6,18].In order to further evaluate the dominant mechanism and parameters of the 1/ noise model for both devices, the normalized inputreferred voltage noise spectral density (LS VG ) as a function of (  −   ) is shown in Figure 4.Both devices show two distinct regions in the associated LS VG .In region I (  −   ≤ −0.1 V), LS VG is independent of (  −   ), which indicates a signature of umber fluctuations.In region II (  −   > −0.1 V), a parabolic dependence of LS VG on (  −   ) is observed, further confirming that correlated mobility  ) and the transconductance to the drain current squared ((  /  ) 2 ) as functions of drain current for HK pMOSFET with and without embedded SiGe S/D.fluctuations was involved.These results mean that the main source of 1/ noise for both devices can be ascribed to the unified model, which incorporates both the carrier number and the correlated mobility fluctuations.Furthermore, the LS VG can be expressed as [19] where  is the tunneling attenuation length for channel carriers penetrating into the gate dielectric,   is the oxide trap density,  is a scattering coefficient, and  0 is the low field mobility.The first term in the parentheses in (1) determines the base LS VG level in our region I and can be described by number fluctuations, in which the LS VG is independent on   −   .The   product is an important parameter related to the base LS VG level.The second term presents the curvature of LS VG versus   −   in region II and can be described by correlated mobility fluctuations.The curvature of parabola is determined by the  0 product.First, as compared with control device, the reduced LS VG level of the embedded SiGe S/D device implies the reduction of  or   .However, previous literature had reported that SiGe S/D process may lead higher   [20,21].In other words, it can only be assumed that the reduced  mainly contributed to the decreased LS VG of SiGe S/D device.The possible mechanism of reduced  of SiGe S/D device is explained as follows.The uniaxial compressive stress-induced valence band offset and more holes tend to exist in top band.Therefore, the out-ofplane effective mass ( *  ) and tunneling barrier height for holes (  ) of SiGe S/D device are both larger than those of control one.As shown in Figure 5, an observed smaller gate current density (  ) in SiGe S/D device confirmed the straininduced increased  *  and   [22].The  is also related to  *  and   by [19,20] where ℎ is reduced Planck's constant.It suggests that strainincreased  *  and   bring a smaller  in SiGe S/D device.The relation between the trap depth (  ) in insulator and  can be revealed according to an equation as   =  ln(1/2 0 ) [23].The RTN measurement is a useful tool for probing the trap location in MOSFET [24][25][26].It will be applied to confirm our observation and assumption of reduced LS VG in the 1/ noise measurement.The   RTN characteristics of both devices as a function of the time show themselves in the form of switching events between two states (not shown here).These switching events are attributed to trapping/detrapping caused by an individual interface defect.The times in the high-and low-current states correspond to carrier capture and emission, respectively.The extracted mean capture time (  ) and mean emission time constant (  ) versus (  −   ) are both presented in Figure 6.It can be found that the SiGe S/D device has the lower values of   and   and the weak dependence of   on   −   , indicating that the trap position is closer to the insulator/semiconductor interface.Figure 7 shows the dependence of   /  on (  −   ) for both devices.From the data obtained for ln(  /  ) dependence on gate voltage, the position of the trap into the oxide (  ) is determined using (3) as follows [14,25]: where  ox is the oxide thickness, and  is the Boltzmann constant.As expectation, the extracted   is 1.68 nm and 1.14 nm for the control device and the SiGe S/D device, respectively.The reduced   in SiGe S/D device is in well agreement on the analysis of 1/ noise (i.e., reduced ) and can be ascribed to the strain-induced higher   for hole.Therefore, though the gate dielectric quality may be degraded by the SiGe S/D process, the traps far away from insulator/semiconductor interface cannot act for capturing carriers, thanks to the reduced , which stemmed from uniaxial compressive strain increasing  *  and   .Consequently, the improvement of LS VG level was observed.On the other hand, in region II, the smaller curvature of LS VG of SiGe S/D device indicates the product of  0 is smaller than that of control device, which can be attributed to the strain-induced lower carrier scattering and higher hole mobility at the same time [27,28].However, it should be noted that the 1/ performance of our HK pMOSFETs will be probably worse than counterparts with traditional SiO 2 insulator [14].This is owing to the  complexity of HK process that led to the higher volume trap densities in gate stacks [29].

Conclusions
In this paper, we have investigated the effect of compressive strain on low-frequency noise in HK pMOSFET.Through RTN measurement, we found that the HK pMOSFET with the embedded SiGe S/D has a shorter distance of the oxide trap position from the insulator/semiconductor interface.This is ascribed to the higher   and smaller  for hole stemmed from uniaxial compressive strain-induced bandgap offset.As a result, the improvement of 1/ noise is observed.It is clear that the better performance of low-frequency noise = 0.25 m/0.04m

Figure 1 :
Figure 1: The   −   characteristics for HK pMOSFET with and without embedded SiGe S/D.

Figure 4 :
Figure 4: Normalized input-referred voltage noise spectral density (LS VG ) versus gate overdrive for HK pMOSFET with and without embedded SiGe S/D.

Figure 5 :
Figure 5: The gate current density (  ) versus gate voltage for HK pMOSFET with and without embedded SiGe S/D.

Figure 6 :
Figure 6: Comparison of the capture time (solid) and emission time (open) for HK pMOSFET with and without embedded SiGe S/D.

Figure 7 :
Figure 7: Plot of capture time (  ) over emission time (  ) versus gate overdrive for HK pMOSFET with and without embedded SiGe S/D.