Gallium Nitride Electrical Characteristics Extraction and Uniformity Sorting

This study examined the output electrical characteristics—current-voltage (I-V) output, threshold voltage, and parasitic capacitance—of novel gallium nitride (GaN) power transistors. Experimental measurements revealed that both enhancedand depletion-mode GaN field-effect transistors (FETs) containing different components of identical specifications yielded varied turnoff impedance; hence, the FET quality was inconsistent. Establishing standardized electrical measurements can provide necessary information for designers, and measuring transistor electrical characteristics establishes its equivalent-circuit model for circuit simulations. Moreover, high power output requires multiple parallel power transistors, and sorting the difference between similar electrical characteristics is critical in a power system.An isolated gate driver detectionmethod is proposed for sorting the uniformity from the option of the turn-off characteristic. In addition, an equivalent-circuit model for GaN FETs is established on the basis of the measured electrical characteristics and verified experimentally.


Introduction
Metal-oxide-semiconductor field-effect transistors (MOS-FETs) have been widely used over the past 30 years.As silicon approaches its performance limits, wide-bandgap semiconductors, such as gallium nitride (GaN) and silicon carbide (SiC), are emerging technologies that can supersede silicon MOSFETs as next-generation power transistors.Novel wide-band III-nitride semiconductor materials are being rapidly developed because of their unique properties, such as high electron mobility, saturation velocity, sheet carrier concentration at heterojunction interfaces, and breakdown voltages [1,2].These properties make III-nitrides feasible for high-power, high-temperature applications.Compared with SiC, GaN has low turn-on and switching losses and is less expensive.In addition, GaN wafers are produced by numerous manufacturers, thus negating any monopoly concerns.Furthermore, GaN has been widely used in light-emitting diodes and wireless applications.GaN power FETs are suitable for high-voltage, high-current, and motor-control applications as well as for industrial automation systems and automotive electronics [3][4][5].
Because both the commercially enhanced-mode (Emode) and depletion-mode (D-mode) GaN FETs manufactured by National Chiao Tung University (NCTU) [6,7] are relatively new types of power transistors, few related studies are available in the literature.In addition, few manufacturers discuss them because commercial applications are not yet prevalent.The electrical characteristics of commercially manufactured power transistors differ because of the differences in cutting, wiring, wire bonding materials and diameters, and packaging.Before using such power transistors in circuit applications, their electrical characteristics must be extracted and sorted to match similar electrical properties in circuit designs.Unfortunately, extracting similar electrical properties is time-consuming and expensive.Thus, rapid and easy extraction of the electrical characteristics of GaN FETs to sort similar electrical properties is essential.

Measurement of GaN Electrical
Characteristics.On the basis of MOSFET and GaN-FET datasheets, the following characteristics were used in this study: (1) breakdown voltage 200 V, rated current 9 A, on-resistance 0.4 Ω, and E-mode MOSFET [16]; (2) breakdown voltage 500 V, rated current 6 A, on-resistance 0.5 Ω, and D-mode MOSFET [17]; (3) breakdown voltage 200 V, rated current 12 A, on-resistance 25 mΩ, and E-mode GaN FET [18]; and (4) D-mode GaN FET manufactured in the laboratory as testing devices.The electrical characteristics measured were   -  characteristics, threshold voltage, and parasitic capacitance.
2.1.1.  -  Characteristic Curve.  -  curve measurements detect the maximum output current of the power transistor when the gate voltage  GS is applied as the fullconduction voltage, and the full-conduction on-state resistance is applied between the drain and source ( DS(ON) ).The characteristic curve reveals the linear and saturation regions of the circuit, where the device can operate properly.According to the test circuit in [19], the output characteristics are drain current   versus drain-source voltage  DS measured under different gate voltages  GS ranging from the gate turnoff to full-on voltage at intervals of 1 V.The  GS range of the Eand D-mode MOSFET is 0 to 12 V and −12 to 0 V, respectively, the  GS range of the E-mode GaN FET is 0 to 5 V, and that of the D-mode GaN FET manufactured by NCTU is −5 to 0 V. Drain voltage generally uses a pulse mode input, which prevents excessive heat that affects the output characteristics.According to the datasheets, test pulse properties for E-and D-mode MOSFETs and E-mode GaN-FETs are a pulse width of 300 s and a duty cycle (duty) ≦2% [16][17][18].In this study, a test pulse width of 300 s, pulse period of 300 ms, and duty cycle of 0.1% were used to measure the   -  curve characteristics of the four aforementioned power transistors.

Threshold Voltage. Threshold voltage (𝑉 TH
) is the minimum gate bias required to turn the device on and produce a drain current specified in the datasheet.In the threshold voltage measurement circuit for E-mode power transistors, the drain and gate terminals of the power transistors are shorted ( DS =  GS ) [16].The voltage to the gate terminal is gradually increased from the turn-off voltage  off (0 V) until the measured current equals the specified drain current.For D-mode power transistors, the drain terminal is connected to a fixed DC voltage source.Similar to the test procedure for E-mode transistors, the voltage to the gate terminal of the D-mode transistor is gradually increased from  off (−5 V) and changes in its drain current   are observed.As specified in the datasheet [17], a DC voltage of 25 V is applied to the drain terminal of D-mode MOSFETs.D-mode GaN FETs, which applying to drain terminal's DC voltage value refer to   -  characteristic curve while the drain voltage attains the saturation region under the power transistor, are fully opened ( GS = 0 V).In this study, laboratorymanufactured D-mode GaN FET saturation voltage was set to the voltage measured from the   -  characteristic curve.The conduction threshold current of E-and D-mode MOSFET is 250 A [16,17] and that of E-mode GaN-FET is 3 mA [18].The laboratory-manufactured D-mode GaN FET has no datasheet for referencing its conduction threshold current.Therefore, to obtain the gate terminal input voltage  GS at which the drain current   increases instantaneously, the experimental measurements of the drain current   are transformed logarithmically [20].The  GS thus obtained is considered the threshold voltage  TH .

Parasitic Capacitance.
A power device analyzer/curve tracer [21] was used to measure the capacitance because it supports the measurement of the three nonlinear capacitances:  GD ,  DS , and  GS .Figure 1 depicts the  GD ,  DS , and  GS measurement circuits, respectively.A multiple frequency capacitance measurement unit with four ports (Hp, Hc, Lp, and Lc) was used for capacitance measurements.Hp and Hc were shorted together (hereafter, CMH), and Lp and Lc were shorted together (hereafter, CML).The CMH outputs an AC test signal through the circuit under test, which is detected by the CML.The CMH operates in the 100 kHz-1 MHz AC frequency range.As specified in the MOSFET and E-mode GaN-FET datasheets,  GS is measured at 100 kHz, and  DS and  GS are measured at 1 MHz; the oscillation level is 30 mV for all measurements.The CML receiving port potential is equivalent to the ground terminal.
The parasitic capacitance  GD is measured using the circuit shown in Figure 1(a).The AC test signal is output from the CMH to the drain terminal, the source terminal is connected to a high-voltage source/monitor unit (HVSMU), and the source terminal grounds the AC signal to the AC guard.Therefore, the AC test signal from  DS to the source terminal is grounded by the AC guard, preventing the signals from being received by the source terminal through the  GS path.When measuring the parasitic capacitance  GD , the HVSMU should provide a  off DC bias relative to the CML gate terminal, and the power transistor should be kept off.Both the enhanced MOSFET and E-mode GaN-FET power  transistor have the same  off (0 V), whereas that of the Dmode MOSFET power transistor is −12 V.However, the   -  curve revealed that the tested D-mode MOSFET turns off at −5 V. Therefore, in this study, −5 V was used as the  off for the D-mode MOSFET power transistor.The  off of D-mode GaN FET is −5 V.Because the source terminal has a bias voltage, − off , the CMH should apply an AC bias voltage in the range  off to 100 − off to drain the terminal.Therefore, the bias  DS voltage of measurement can range from 0 to 100 V.The parasitic capacitance  DS is measured using the circuit shown in Figure 1(b).The circuit is similar to that used to measure  GD ; the only difference is that the gate terminal was changed to the source terminal to connect the CML.The CMH outputs an AC test signal to the drain terminal and receives an AC test signal from the CML by connecting CML to the source of the device under test.The gate terminal grounds the AC guard to prevent the AC test signals from being received by the source terminal through the  GD and  GS paths.To ensure that the power transistor remains off during the measurement, the DC voltage  off is applied to the gate terminal.The CMH gradually increases the AC bias voltage from 0 to 100 V; therefore, the parasitic capacitance measurement  DS is in the  DS voltage range of 0-100 V.
The parasitic capacitance  GS is measured using the circuit shown in Figure 1(c).The CMH outputs an AC test signal to the gate terminal, and the CML receives the signal by connecting to the source terminal.Because the CMH has a  off bias, the power transistor is kept off.To prevent the signals from being received by the source terminal through the  GD and  DS paths, the drain terminal is grounded to the AC guard.The HVSMU provides DC voltage in the range of 0-100 V; therefore, parasitic capacitance  GS is measured at different  DS voltages in the range of 0-100 V.  2. The gate drive voltage for the E-mode GaN FET gate-to-source voltage is  ISO −  ISO , and the  GS for D-mode GaN FET gate drive voltage is − ISO to  ISO .The difference between the gate drive circuits for E-and D-mode GaN FETs is that the input supply voltages for the isolated gate driver amplifier are (+ ISO )−( ISO ) and ( ISO )−(− ISO ), respectively.The external gate drive signals of the isolated gate drive circuit for the E-mode GaN FET is [0 to + ISO ] relative to the ground (Gnd).Through the fast optical coupling IC, the signal is isolated and converted to [0 to + ISO ] relative to  ISO .Finally, the isolated signal is amplified through the gate driver IC to drive the E-mode GaN FET.Similarly, the gate drive circuit for D-mode GaN FET is isolated to produce the gate signal [− ISO −  ISO ] relative to  ISO to drive the FET.

Isolated Gate Drive Detection.
The isolated gate drive signal waveform can be measured by an oscilloscope to distinguish the waveforms of the turn-off impedance  DS(off) when GaN FETs are in the turn-off state.The proposed detection method is a relatively simple screening method to sort similar electrical characteristics of GaN FETs; by observing the switching waveforms, external stray capacitance in the circuit boards and internal parasitic capacitance in the transistors can be detected.The simple and accurate GaN FET model established on the basis of the measured electrical characteristics can be verified through experimental measurements of the isolated gate drive signal waveforms.
The proposed isolated gate drive detection circuit is illustrated in Figure 2, and the drive signal for the E-mode GaN FET is shown in Figure 3. Voltages  1 ,  4 , and  5 were measured relative to the Gnd;  2 and  3 were measured relative to the isolated supply ground  ISO .The drain terminal of the E-mode GaN FET test circuit connects to the power supply voltage  DD relative to the Gnd.When the gate-tosource voltage of the E-mode GaN FET is  ISO , it turns on and shorts the drain and source terminals.Ideally, the source terminal voltage relative to the Gnd should be promoted to  DD .The source terminal of the GaN FET and the isolated power source terminal  ISO are connected, indirectly causing  ISO and GaN FET Gnd to turn on and off; therefore,  ISO has a relative floating voltage of  DD .When the gate terminal voltage of the GaN FET relative to the source terminal voltage is  ISO , the E-mode GaN FET turns on, the isolated power supply ground  ISO relative to the Gnd is  DD , and the voltage between the GaN FET gate terminal and the Gnd is  DD + ISO .When the gate terminal voltage relative to the source terminal is 0 V, the E-mode GaN FET turns off, the gate and source terminals are open, and  ISO and Gnd are 0. Because the GaN FET turns off, the drain terminal voltage  DD no longer offers voltage to  ISO .The floating voltage  DD discharges through circuit stray capacitance  stray and load resistance   .Therefore,  ISO floating voltage discharges from  DD at the speed of the resistor-capacitor time constant until the next pulse width modulation (PWM) signal to the gate-tosource voltage is  ISO , which turns the GaN FET on again.When the drain terminal voltage  DD is supplied to  ISO , the parasitic capacitance  ISS can be recharged to  DD +  ISO .The higher the PWM drive signal frequency entering the gate terminal, the more stable the  ISO in maintaining  DD .When the PWM signal is no longer sent to the gate terminal and the GaN FET remains off for a sufficient period,  DD discharges to 0 V through circuit stray capacitance  stray [22] and load resistance   , as shown in Figure 2 ( 5 ).Concurrently, Gnd drops to 0 V. Compared with the turn-off impedance of Si MOSFETs, the turn-off impedance  DS(off) of the GaN FET is low.Therefore, the leakage current offers a load resistance   to produce voltage  (off) .The turn-off impedance  DS(off) of the GaN FET can be obtained by observing the  (off) variance.
The D-mode GaN FET signal is depicted in Figure 4.When the gate-to-source terminal voltage of the D-mode GaN FET is 0 V, because it is typically turned on, its drain and source terminals are short.In this case, the source-to-ground Gnd voltage should be increased to the power supply voltage  DD , and the GaN FET gate-to-ground Gnd voltage should be  DD .When the gate-to-source terminal voltage is − ISO , the transistor turns off.Concurrently, the gate-to-ground Gnd becomes  DD − ISO .The  ISO voltage  DD discharges through the circuit stray capacitance  stray [22] and the load resistance   , as shown in Figure 2 ( 5 ), until the next PWM to the gateto-source terminal voltage is 0 V, which turns the GaN FET on again.The drain terminal voltage  DD provides voltage to  ISO .When the gate terminal PWM signal ceases and the GaN FET remains off for a sufficient period, the gateto-ground Gnd voltage discharges through the circuit stray capacitance and resistance to 0 V.The condition of the Dmode GaN FET is the same as that of the E-mode GaN FET.The turn-off impedance  DS(off) of D-mode GaN FET is smaller than that of Si MOSFET; therefore, the leakage current offers a load resistance   to produce voltage  (off) .The relationship between the turn-off impedance  DS(off) , leakage current, and voltage  (off) is discussed later.

Isolated Gate Driver Circuit Model.
To make the device model adaptable to and suitable for a system-level simulation, a subcircuit model was developed using the measured characterization results as the parameters of the model [23].A simplified isolated gate driver detection circuit architecture is shown in Figure 5(a).A voltage probe is used to measure the voltage between the gate terminal and the ground.When  GS is 0 V (to turn the E-mode GaN FET off) or − ISO (to turn the D-mode GaN FET off), the E-or D-mode GaN FETs are equivalent to a turn-off resistance  DS(off) , which can be used to evaluate the turn-off capacity of the GaN FET.In this test, with a known probe resistance value   and by applying the Kirchhoff laws, the current through the power supply voltage  DD at resistances  DS(off) and   is obtained as the leakage current  DSS , which can be described as follows: The leakage current  DSS flows through the voltage probe and produces  (off) as follows: By substituting (1a) into (1b), the  DS(off) impedance can be derived as follows: A simplified simulation of the isolated gate drive detection circuit is shown in Figure 5 Linear region: Saturation region: where   is the transduced value and  is the short-channel width-modulation slope coefficient in the saturated region, which is initially set to 0. The sign of  TH determines the mode: positive is for E-mode and negative is for D-mode.
Using the established Level 1 MOSFET   -  characteristics model equations to describe the GaN FET current value in the saturation region reveals a large difference between experimentally measured and simulated data.Therefore, referring to a smoothing equation, the coefficient 1/2 in (3b) is replaced with 1/3 and that in (3c) is replaced with 2/3.The smoothing equation ( 4) is used to smoothen the   -  characteristic curve in the linear and saturation regions; the  GS −  TH voltage value is modified to  GS eff and substituted in (5a) and (5b).The + and − signs denote the D-and E-modes of the GaN FET, respectively, which complies with the   -  characteristics of the GaN FET model.The  value impacts the degree of smoothness between the linear and saturated regions; the higher the value is, the smoother the curve is [24].The smoothing equation is as follows: After smoothening, the GaN FET   -  characteristic equations for the linear and saturation regions are depicted as follows: Linear region ( DS ≤  GS eff ): Saturation region ( DS >  GS eff ): SPICE simulation software [25] was used to simulate the electrical characteristics and to verify the measured gate drive signals.The Shenai model [23] was used and the builtin Level 1 MOSFET capacitance model was replaced with external capacitances.The measured gate-source capacitance was relatively independent of  DS voltage, and a constant measured capacitance  GS was used in the circuit model.The  GD and  DS can be described using the following equations: where  GD0 is the zero-bias gate-to-drain capacitance,  DS0 is the zero-bias drain-to-source capacitance,  GD is the gateto-drain voltage,  DS is the drain-to-source voltage,   is the junction built-in potential, and  is the junction grading coefficient.The parameters   and  were adjusted to obtain the optimal fit with the measured capacitance data.Moreover, the effect of external couple capacitances on  GS during turnoff is considered.Figure 8 plots the  DS(ON) of the four power transistors.In the enhanced MOSFET,  DS(ON) at  GS = 10 V,  DS = 1.44 V, and  DS = 4.5 A is approximately 1.44/4.5 = 0.32 Ω, which is under the maximum value specified in the datasheet (0.4 Ω).

Results and Discussion
In the D-mode MOSFET,  DS(ON) at  GS = 0 V,  DS = 1.66 V, and  DS = 3 A is approximately 1.66/3 = 0.55 Ω, which is close to the value specified in the datasheet (0.5 Ω).Although the D-mode MOSFET  GS is 0 V, it conducts current but not at full conduction.When  GS is 5 V,  DS is 30 V and the output current   is 35 A. When  GS is −2 V, the power transistor turns off and the output current   is close to zero.GaN FET output characteristic variation is considerably large compared with that of the MOSFET.The output current value exhibits drift phenomena in different E-mode GaN FET samples when the inputs  GS and  DS are the same.The experimental results show that the linear region of the onresistance  ON is approximately 0.025-0.03Ω.When  GS is 5 V and the average output current   is 6 A, the average voltage  DS is 0.18 V; therefore, the average on-state resistance  ON is 0.18/6 = 0.03 Ω, which exceeds the datasheet value of 0.025 Ω.The D-mode GaN FET on-resistance  ON is approximately 0.25-0.30Ω.When  GS is 0 V and  DS is 1 V,   is 3.87 A; therefore,  ON is 1/3.87 = 0.26 Ω.
Equations (5a) and (5b) are used to establish the current source model of a transistor.The output voltage  DS of the E-mode GaN FET is increased from 0 to 3 V at intervals of 0.1 V, and the gate input voltage is increased from 0 to 5 V at intervals of 1 V; the output voltage  DS of the D-mode GaN FET is increased from 0 to 10 V at intervals of 0.5 V, and the gate voltage is increased from −5 to 0 V at intervals of 1 V.
The waveforms are shown in Figures 7(c) and 7(d) as solid lines with circles; the simulated characteristics are similar to the measured characteristics (dashed lines).Drain current V DS (V)

NCTU-GaN
V DS (V)  DS (-axis) at a particular voltage  DS (-axis) can be obtained from the simulated waveform.In addition to the on-resistance  ON characteristics, the saturation voltage of the D-mode GaN FETs exhibits variance.The experimental results show that the average saturation voltage is at  DS = 7 V and that the maximum saturation current is between 16 and 18 A. The conduction resistance  DS(ON) of the Dmode GaN FET is 0.26 Ω, which is smaller than those of the two MOSFET power transistor (0.32 and 0.55 Ω) but much larger than that of the E-mode GaN FET (0.03 Ω).In the future,  DS(ON) of the D-mode GaN FET can be improved using internal or external parallel methods [6,7]; therefore, uniform performance should be sorted.

Threshold Voltage.
The measured threshold voltage  TH is plotted in Figure 9.The conduction threshold current of the MOSFET power transistor is defined as 250 A.
From the experimental results of the enhanced MOSFET, the threshold voltage  TH is 3.21 V, which is in the range specified in the datasheet (2-4 V).Furthermore, the conduction threshold current of the D-mode MOSFET is 250 A; therefore, the gate threshold voltage  TH is −2.98 V, which is in the range specified in the datasheet (−4 to −2 V).From the information in the manual, E-mode GaN FET conduction threshold current is defined as 3 mA.
In Figure 9(a), when the output current of the E-mode GaN FET is 3000 A, the gate threshold voltage  TH is 1 V, which is in the range specified in the datasheet (0.7-2.5 V).The output current   of the D-mode GaN FET is plotted logarithmically in Figure 9(b).Near  GS = −3.9V, the output current   rises rapidly.Hence, this  GS voltage is defined as the threshold voltage of the D-mode GaN FET.The threshold voltage  TH of the E-mode GaN FET is much lower than that of the MOSFET.Output characteristics

Isolated Gate Drive Detection.
A turn-off voltage of 0 V is used for the E-mode GaN FET; therefore, the full-conduction voltage is limited to 5.5 V.For the D-mode GaN FET, the used turn-off voltage is −5 V, and full-conduction voltage is limited to 2 V. Hence, the driving voltage for the E-mode GaN FET gate-to-source voltage is set to 0−5 V; in other words,  ISO is set to 5 V, and the D-mode GaN FET gate source driving voltage is set to −5 to 0 V.At driving voltages of 0-5 V and −5 to 0 V, the E-and D-mode MOSFET waveforms can be contrasted.Regardless of the MOSFET mode, the voltage probe was used to measure the voltage between the gate terminal and the ground terminal.The E-mode MOSFET waveforms are the same as the ideal isolated gate drive circuit detection signal, as depicted in Figures 3 and 4; the gate voltage when turned on is +29 V and decreases to 0 V when turned off (Figure 11(a)).The D-mode MOSFET gate voltage waveform is +24 V, which decreases to 0 when turned off (Figure 11(b)).When measuring the E-mode GaN FET, the gate voltage is +29 V when turned on, but a difference in voltage level exists between the gate and the ground.The large change in the voltage level is in the 0-24 V range, as shown in Figure 12(a).D-mode GaN FETs exhibit the same phenomenon, as shown in Figure 12(b).The differences are caused by the turn-off impedance  DS(off) .The larger the turnoff impedance is, the smaller the leakage current is; the across voltage  (off) is small, and the difference between sourceto-ground voltage value is close to 0. Conversely, when the turn-off impedance is small, the leakage current is large, and the source-to-ground voltage approaches +24 V. Therefore, the turn-off ability of GaN FETs can indirectly screen device uniformity.Moreover, the impedance value can be quantified.When  GS = 5 V, the E-mode GaN FET turns on.The gate-to-ground voltage is +29 V; when  GS = 0 V, the Emode GaN FET turns off, which is equivalent to the turnoff resistance  DS(off) ; the voltage probe resistance is   .When the Kirchhoff circuit laws are applied, the power supply voltage  DD through  DS(off) and   generate the leakage drain current  DSS .Through the isolated gate drive circuit architecture, the voltage probe resistance   is 10 MΩ and power supply voltage  DD is 24 V.The  (off) values for the two modes are 13.6 V and 23.0 V, as shown in Figure 12(a).Substituting these values into (2),  DS(off) is obtained as 7.647 and 0.435 MΩ.Using a digital multimeter in series with the source terminal and the voltage probes (  ) to measure the GaN FET device during the turn-off state, the leakage currents  DSS are obtained as 1.340 and 2.365 A.By substituting  (off) in (1a), leakage currents  DSS are obtained as 1.36 and 2.30 A, which are similar to the measured values.
Next, the gate-to-ground voltage waveform of the Dmode GaN FET is measured.When  GS is 0 V, the D-mode GaN FET drain and source conducts and shorts, and the source terminal voltage is +24 V.Because  GS = 0 V, the gate terminal voltage is +24 V; when  GS = −5 V, the GaN FET is off, because the resistance of the D-mode GaN FET  DS(off) is not large enough; therefore, leakage current flows, and the source terminal voltage relative to ground cannot be reduced to 0 V. Next, the turn-off voltage of the D-mode GaN FET is measured using the 10 MΩ voltage probe; the value is always 19 V.The turn-off impedance  DS(off) is much lower than 10 MΩ; therefore, the voltage probe is adjusted to 1 MΩ to repeat the experiments. (off) is in the 0-19 V range. DS(off) and voltage probe   = 1 MΩ divide the voltage, assuming that the probe is measured as  (off) voltage.From (1a), (1b), and (2), the leakage current  DSS and turn-off impedance  DS(off) can be obtained.
The waveform variability of the D-mode GaN FET is similar to that of the E-mode GaN FET, as shown in Figure 12(b).The D-mode GaN FET under a voltage probe   = 1 MΩ varies in the 16-20 V range.From (2),  DS(off) of the D-mode GaN FET is 463.4 kΩ when  (off) is 16.4 V and 904.8 kΩ when  (off) is 12.6 V.However, when  (off) exceeds 24 − 5 = 19 V, the turn-off impedance is insufficient and the transistor does not turn off.
In the E-mode GaN FET, the threshold voltage  TH of the output characteristic curve - model parameter is set to 1 V and   is set to 24.An external capacitor is used as listed in Table 2.In the isolated gate driver circuit architecture, the voltage probe resistance   = 10 MΩ, power supply voltage  DD = 24 V, and measuring voltage  (off) = 13.6 V. From (2),  DS(off) impedance is derived as 7.647 MΩ when  (off) is 13.6 V; therefore, when E-mode GaN FET turns off, the drain-to-source  DS(off) is equivalent to a 7.647 MΩ resistor.  is the internal voltage probe resistance, which is 10 MΩ at 10x magnification.In the D-mode GaN FET, the threshold voltage  TH of its - output characteristic curve model is −3.9 V and   is 2.1.The external capacitor is used as parasitic capacitance.The turn-off impedance  DS(off) of the experimental device using the 10x magnification voltage probe is much lower than 10 MΩ.Hence, a 1x (1 MΩ) probe is used to measure (  = 1 MΩ); the power supply voltage  DD = 24 V and the measured  (off) voltage = 12.6 V. From (2), when  (off) voltage is 12.6 V,  DS(off) is 904.8 kΩ.The equivalent turn-off resistance  DS(off) between the drainsource is equivalent to 904.8 kΩ.SPICE circuits are established through the equivalent model described in Figure 5.The gate resistor uses 100 Ω   , and the E-mode GaN FET gate terminal wave signal  GS voltage is 0-5 V, whereas the D-mode GaN FET  GS is −5 to 0 V. Gate pulse width, period, and frequency of the PWM signal are 100 s, 500 s, and 2 kHz, respectively.The numerical analysis software predicts that the gate drive circuit board has external drain-source stray capacitance  stray and that the actual measurements of waveform segments have a slower falling slope.Because of stray capacitance  stray parallel to drain-to-source and gate-to-drain, the turn-off  GS slope falls slowly in the waveform.The estimates of the stray capacitance  stray value are 2 nF.The GaN FET gate detection simulation parameters are shown in Table 2.  than that of the enhanced MOSFET; a smaller  RSS capacitance value indicates that the Miller plain area is relatively short and that the switching time is shorter.Compared with the turn-off resistance of different samples, the electrical characteristics of each MOSFET device are highly consistent, whereas those of GaN FET exhibit less uniformity.GaN FETs are currently under development, and the electrical characteristics of each component are relatively unstable; the variability is larger than that in MOSFET.This study established a standardized electrical measurement procedure that provides necessary information for designers.In addition, a simple and accurate GaN FET model was established on the basis of the measured electrical characteristics.The simulation waveforms can be used to obtain information on GaN FET's internal parasitic capacitance, turn-off impedance  DS(off) , and stray capacitance  stray in the inverter circuit board.The proposed GaN FET isolated gate drive circuit screening method by  DS(off) detection provides a simple uniformity sorting method.The results show that the higher the off-state voltage  (off) is, the smaller the turn-off voltage  DS(off) is; in other words, the device has a lower  DS(off) .The leakage current in GaN devices is much larger than that in MOSFET devices in the turn-off state.The off-resistance of MOSFET is generally larger than 10 MΩ.By contrast, the offresistance of E-mode GaN FETs is larger than 1 MΩ, whereas those of D-mode GaN FETs are approximately in the 0.5-1.5 MΩ range.Devices with the same off-state voltage  (off) perform similarly.Moreover, the larger the turn-off resistance  DS(off) is, the closer the characteristics are to those specified in the datasheet.Professor Edward Yi Chang of NCTU for supporting GaN devices, Professor Stone Cheng of NCTU for supporting package technology, and National Nano Device Laboratories, Hsinchu, Taiwan, for their very helpful suggestions and technical support.

Figure 3 :
Figure 3: Detection drive signal for E-mode transistor.

Figure 4 :
Figure 4: Detection drive signal for D-mode transistor.

Figure 5 :Figure 6 :
Figure 5: Simplified schematic of gate drive detecting circuit: (a) simplified schematic and (b) simplified equivalent model.

3. 1 .
-  Characteristic Curve.E-and D-mode GaN FET devices under test are shown in Figure6.The tested Dmode GaN FET chip is 80 mm in size and is packaged in the TO-3P form.Figure7depicts the measured   -  characteristics of the four power transistors.Solid lines represent the waveforms specified in the datasheets, dotted lines represent the measured waveforms, and solid lines with circles represent the SPICE-simulated waveforms.The measured   -  characteristics of the E-and Dmode MOSFET waveforms are similar to those specified in the datasheet.The on-resistance  DS(ON) at a specific turnon gate voltage  GS and drain current  DS can be extracted directly from the output characteristic curves.

Figure 8 :Figure 9 :
Figure 8: On-resistance of the four power transistors.
Figures 13 and 14  present the E-and D-mode GaN FET gate detection simulation circuit waveform as shown in black line and measurement waveform as shown in orange

Figure 13 :
Figure 13: Simulation results of E-mode GaN FET.

Figure 14 :
Figure 14: Simulation results of D-mode GaN FET.

Figure 15 :
Figure15: The turn-off voltage  (off) and the corresponding  DS(off) of E-mode GaN FETs.
(b).The simplified simulation circuit consists of the controlled signal source, E-or D-mode GaN FET current source, the isolated power supply ground  ISO , ground Gnd, the parasitic capacitances  GS ,  GD , and  DS , turn-off impedance  DS(off) , and voltage probe resistance   .The turn-off resistance  DS(off) and voltage probe resistance   connect together and, with the applied voltage  DD and ground Gnd, form a loop that can use the Kirchhoff voltage law to estimate the leakage current  DSS .The  DS current source is extracted from the   -  characteristics.The   -  characteristic curve of the GaN FET follows the

Table 1 :
Comparison of datasheet and measured characteristics.