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Dual edge triggered (DET) techniques are most liked choice for the researchers in the field of digital VLSI design because of its high-performance and low-power consumption standard. Dual edge triggered techniques give the similar throughput at half of the clock frequency as compared to the single edge triggered (SET) techniques. Dual edge triggered techniques can reduce the 50% power consumption and increase the total system power savings. The low-power glitch-free novel dual edge triggered flip-flop (DET-FF) design is proposed in this paper. Still now, existing DET-FF designs are constructed by using either C-element circuit or 1P-2N structure or 2P-1N structure, but the proposed novel design is designed by using the combination of C-element circuit and 2P-1N structure. In this design, if any glitch affects one of the structures, then it is nullified by the other structure. To control the input loading, the two circuits are merged to share the transistors connected to the input. In the proposed design, we have used an internal dual feedback structure. The proposed design reduces the delay and power consumption and increases the speed and efficiency of the system.

Today, the flip-flops are widely used for data storage. The performance and fault tolerance ability of the devices are precisely affected by the flip-flops reliability, speed, and power consumption. As a result, this is needed to design the flip-flops for lowest power consumption, propagation delay, area, and highest reliability with fault tolerance ability. Present studies have shown that device scaling reduces the device capacitances and the supply voltage requirements, and circuit becomes more vulnerable to the glitches. When particles touch the drain side of a MOSFET, electron hole combinations are generated. The reverse biased electric field produces a drift transient current [

Low-power consumption may be obtained efficiently by voltage supply scaling. In CMOS designs, power consumption due to the glitches cannot be ignored as the portion of power consumption varies somewhat between 9% and 38% [

The rest part of this paper is arranged as follows. Section

Dual edge triggered flip-flops provide the equal data rate as single edge triggered flip-flops at the half of the clock frequency, which leads to the reduction in power dissipation of digital synchronous logic designs [

DDR-FF (LM_C) design [

TSPC design [

Figure

LG_C design [

Generally, the C-element structures are used to reduce the switching activity. The 2P-1N three-transistor structure [

(a) 2P-1N structure and its truth table. (b) C-element circuit and its truth table.

Present day, the main goal of the researchers is to achieve small area, low power, and high speed in the field of VLSI designing. Therefore, several approaches have been considered by the researchers in VLSI applications to achieve these motives. We have designed a low-power glitch-free novel dual edge triggered flip-flop circuit design, as shown in Figure

Proposed design with 2P-1N structure and C-element circuit.

Consequently, we have presented a novel robust low-power glitch-free dual edge triggered flip-flop design by mixed combination of 2P-1N and C-element structures which can work accurately at low power supply and provides the totally glitch-free output which can increase the system efficiency. The proposed circuit model consumes less power and provides glitch-free output. The working of the proposed design is as follows: case 1, the glitch either filter out or propagate to the output node Q; case 2, if glitch propagates to the output node Q, then it is filtered out through the feedback path. We just explain how this design avoids the glitches which may occur at the input node from the preceding combinational circuits.

Initially, let the nodes

Now, let the nodes

Now, let the nodes

Now, let the nodes

The proposed low-power glitch-free novel dual edge triggered flip-flop design is performed through the SPICE simulator with Predictive Technology Model (PTM) 22 nm CMOS technology [

In the higher technologies, the operating voltage decreases and the frequency increases. Therefore, we have taken 1 V operating voltage, and the frequency is fixed to 500 MHz. When the operating frequency is high enough, the output will not reduce. The glitch-free novel dual edge triggered flip-flop design is simulated through the SPICE simulator, and the results are calculated and verified. The performance evaluation results are reported in Table

Result analysis of different dual edge triggered flip-flops.

DET-FFs | Reference [ |
Reference [ |
Reference [ |
Proposed design |
---|---|---|---|---|

_{avg. cons.} ( |
8.094 | 7.825 | 8.988 | 3.049 |

_{
p(D-Q)} (ps) |
72.872 | 65.536 | 84.297 | 26.995 |

_{
p(CLK-Q)} (ps) |
55.021 | 43.213 | 63.281 | 25.896 |

PDP (fJ) | 0.589 | 0.513 | 0.758 | 0.082 |

Number of transistors | 28 | 38 | 28 | 18 |

Comparative analysis of average power consumption, propagation delay, and area (number of transistors) for different glitch-free dual edge triggered flip-flop designs are shown in Figure

Power, delay, and area comparisons of different DET-FF designs.

The propagation delay analysis of glitch-free novel dual edge triggered flip-flop is presented in Figures

Delay analysis of proposed DET-FF design with different frequencies.

Delay analysis of proposed DET-FF design with different temperatures.

Due to the power supply voltage reduction, power consumption decreases but propagation delay increases. The propagation delay increases with the increase in the temperature (from −100°C to +100°C), as indicated in Figure

The average power consumption analysis of glitch-free novel dual edge triggered flip-flop is presented in Figures

Average power consumption analysis of the proposed DET-FF design with different frequencies.

Average power consumption analysis of the proposed DET-FF design with different temperatures.

We have presented a low-power glitch-free novel dual edge triggered flip-flop which is designed with the mixed combination of 2P-1N and C-element structures. The glitch-free novel dual edge triggered flip-flop design is the novel and unique design because it is constructed by using two fault resistant structures. If any glitch affects one of the structures, then it is corrected by the other structure. The glitch-free novel dual edge triggered flip-flop provides the totally glitch-free output and can increase the system efficiency. The presented novel design can reduce the 50% power consumption and contribute to the total system power savings. By using the fault resistant structure and internal dual feedback structure proposed design obtained robust and static operation. To reduce the input loading, the two structures are merged to share transistors connected with the data input. The proposed glitch-free novel dual edge triggered flip-flop has the lowest power consumption and lowest power delay product (PDP) as compared to the existing dual edge triggered flip-flop designs [

The authors declare that they have no conflicts of interest.