Journal of Sensors
Volume 2017 (2017), Article ID 4078240, 9 pages
https://doi.org/10.1155/2017/4078240

Research Article

High Frequency InGaAs MOSFET with Nitride Sidewall Design for Low Power Application

Jiongjiong Mo, Hua Chen, Zhiyu Wang, and Faxin Yu

School of Aeronautics and Astronautics, Zhejiang University, Zheda Road 38, Hangzhou 310027, China

Correspondence should be addressed to Hua Chen; chenhua@zju.edu.cn

Received 1 October 2016; Accepted 2 February 2017; Published 20 February 2017

Academic Editor: Hao Gao

Copyright © 2017 Jiongjiong Mo et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract.

devices have been widely researched for low power high frequency applications due to the outstanding electron mobility and small bandgap of the materials. Regrown source/drain technology is highly appreciated in InGaAs MOSFET, since it is able to reduce the thermal budget induced by ion implantation, as well as reduce the source/drain resistance. However, regrown source/drain technology has problems such as high parasitic capacitance and high electric field at gate edge towards the drain side, which will lead to large drain leakage current and compromise the frequency performance. To alleviate the drain leakage current problem for low power applications and to improve the high frequency performance, a novel Si₃N₄ sidewall structure was introduced to the InGaAs MOSFET. Device simulation was carried out with different newly proposed sidewall designs. The results showed that both the drain leakage current and the source/drain parasitic capacitance were reduced by applying Si₃N₄ sidewall together with InP extended layer in InGaAs MOSFET. The simulation results also suggested that the newly created “recessed” sidewall was able to bring about the most frequency favorable characteristic with no current sacrifice.

1. Introduction

InGaAs MOSFET technology has been widely investigated for low power applications [1–7]. By using the regrown source/drain method, very low source/drain ohmic contact can be obtained [8–11] with highly doped material and reduced gate-source/gate-drain distance. However, high source/drain parasitic capacitance prohibits the InGaAs MOSFET from boosting the frequency performance due to the high- dielectric layer between the gate contact and the regrown source/drain contact. Besides, while high electron mobility is appreciated, III-V MOSFETs suffer from large drain leakage current when high electric field is applied [12–16]. To address these problems, a novel Si₃N₄ sidewall was introduced between the gate contact and the regrown source/drain. It is able to reduce the parasitic capacitance and the drain leakage current under high electric field. Different Si₃N₄ sidewall structures were proposed including one normal sidewall indicated as “spacer 1” and the other “recessed” sidewall together with InP extended layer, indicated as “spacer 2.” Device simulation was carried out using Atlas [17] to evaluate drain leakage current and frequency performance. The “spacer 1” is able to effectively reduce the drain leakage current, while the “recessed spacer 2” can significantly decrease the parasitic capacitance without compromising the on-state performance.

2. Design Consideration and Motivation

In this paper, we proposed InGaAs MOSFET structures with Si₃N₄ sidewall. Standard regrown source/drain MOSFETs only have one high- layer between the gate metal and the source/drain, which forms high parasitic capacitances and according to , prohibiting the device from attaining high frequency performance. To reduce the parasitic capacitance, we propose to insert a novel Si₃N₄ sidewall layer between the gate metal and source/drain. The effective dielectric constant for the parasitic capacitance was therefore lowered and the dielectric thickness was increased, leading to smaller parasitic capacitance. Besides, InGaAs MOSFETs suffer from high drain leakage current [18–20], especially with the gate length scaling, due to the band-to-band tunneling effect caused by the high electric field at gate edge towards the drain side [21–23]. To deal with the band-to-band tunneling problem, different solutions have been proposed, including adding larger bandgap material between the channel and regrown source/drain and lowering the doping level of the interfacial layer between the channel and the regrown source/drain. Here we propose a novel approach to solve the band-to-band tunneling problem by introducing a sidewall structure. With the insertion of the sidewall along the source/drain, the electric field would be modulated thus relieving the leakage problem. As a side effect, however, the insertion of the Si₃N₄ would enlarge the gate-to-source and gate-to-drain distance and thus increase the source/drain access resistance. Another Si₃N₄ sidewall structure “spacer 2” was then proposed to avoid the access resistance increase.

3. Simulation and Analysis

Device simulation without sidewall and with two different sidewalls was carried out using basic InGaAs MOSFET structure, and the three different structures were shown, respectively, in Figures 1(a), 1(b), and 1(c). The MOSFET structure consisted of a 10 nm In0.53Ga0.47As channel on top of a In0.52Al0.48As buffer layer, grown on InP substrate. The regrown source/drain consisted of a thin InP layer and a 70 nm highly doped InGaAs layer. A 7 nm HfO₂ layer was used as high- gate oxide as well as the insulating layer between the gate contact and the regrown source/drain contact. Two sidewall structures were studied: one is a normal sidewall along the InP/InGaAs side, which is indicated as “spacer 1” and shown in Figure 1(b), and the other is a novel “recessed” sidewall along the InGaAs side only, aligned to the extended InP head, which is indicated as “spacer 2” and shown in Figure 1(c). Basic simulation models such as “BGN” (Bandgap Narrowing model), “CVT” (Lombardi model including , , and effects), and “SRH” (Shockley-Read-Hall model) were used, and the sidewall processing damage was not considered during the simulation.

(a)

(b)

(c)

Figure 1: InGaAs MOSFET structures (a) without sidewall, (b) with sidewall “spacer 1,” and (c) with sidewall “spacer 2” for Atlas simulation.

Electric field simulation results for devices without sidewall and with Si₃N₄ sidewall were shown in Figures 2(a) and 2(b), respectively. The highest electric field was found at the gate edge towards the drain side. Comparing the two structures, the device with sidewall had a smaller electric field (4.4 10⁷ V/cm) than the device without sidewall (4.8 10⁷ V/cm), which is favorable for reducing drain leakage current. From the transfer characteristics shown in Figure 3, where the black curve represents the device without spacer, the blue curve represents the device with “spacer 1,” and the pink curve represents the device with “spacer 2”; the device with sidewall “spacer 1” reduced the drain leakage current by more than 2 orders than the one without sidewall from 10⁻⁸ A to 10⁻¹⁰ A, although the drain saturation current was compromised due to the increased access resistance induced by the sidewall, as indicated in the inserted illustration in Figure 1(a). Sidewall “spacer 2” showed almost the same transfer characteristic as that without sidewall, since Si₃N₄ was on top of the extended InP drain layer, and its electric field modulation capability was screened by the InP layer. The parasitic capacitance simulation results were shown in Figure 4(b), where the set of solid curves represent the values and the set of open curves represent the values, showing that and were significantly reduced from 3 10⁻¹⁵ F/μm to 1 10⁻¹⁵ F/μm by the Si₃N₄ sidewall according to , where ɛ is the dielectric constant of the sidewall, and is the dielectric thickness. The dielectric constant of Si₃N₄ is much smaller ( = 4–7) than that of HfO₂ ( = 16–22), which increased the effective dielectric constant for parasitic capacitance. Besides, the insertion of 10 nm Si₃N₄ added up to the total dielectric thickness and thus further reduced the parasitic capacitance. The sidewall “spacer 2” showed slightly higher parasitic capacitance than sidewall “spacer 1” since only the recessed part along the InGaAs source/drain side has sidewall, and there existed only high- HfO₂ between gate electrode and InP source/drain. Figure 4(a) showed the gain simulation results, where the set of solid curves represent the current gain values and the set of open curves represent the unilateral power gain values, from which the cut-off frequency and the maximum oscillation frequency can be extracted. While the current gain was smaller for device with sidewall “spacer 1” due to its higher access resistance and smaller transconductance (), the unilateral power gain for the device with sidewall “spacer 1” caught up with the one without sidewall due to reduced and increased capacitance influence (). The device with sidewall “spacer 2” showed the highest current gain and unilateral power gain among the three structures since the recessed sidewall helped to decrease the parasitic capacitance effectively while it barely added up to the access resistance.

(a)

(b)

Figure 2: Electric field simulation of InGaAs MOSFET (a) without sidewall and (b) with sidewall “spacer 1.”

(a)

(b)

Figure 3: (a) and (b) characteristics of InGaAs MOSFET with sidewall “spacer 1,” “spacer 2,” and without sidewall.

(a)

(b)

Figure 4: (a) Current gain, unilateral power gain versus frequency (solid: current gain ; open: unilateral power gain ), and (b) parasitic capacitances and versus frequency (solid: ; open: ) of InGaAs MOSFET with sidewall “spacer 1,” “spacer 2,” and without sidewall.

The influence of the thickness of both “spacer 1” and “spacer 2” sidewalls was studied, verified from 2 nm to 10 nm. The characteristics for “spacer 1” were shown in Figure 5 for different Si₃N₄ sidewall thickness, where the black curve represents the device with spacer 1 of 2 nm, the red curve represents the device with spacer 1 of 4 nm, the green curve represents the device with spacer 1 of 6 nm, the blue curve represents the device with spacer 1 of 8 nm, and the pink curve represents the device with spacer 1 of 10 nm. It is observed that the drain leakage current was improved from 10⁻⁸ A, 3 10⁻¹⁰ A, 1 10⁻¹⁰ A, and 7 10⁻¹¹ A to 4 10⁻¹¹ A with increasing Si₃N₄ thickness. This could be due to the effective electric field modulation at gate edge towards the drain side by the use of Si₃N₄ sidewall. The current gain and unilateral power gain were shown in Figure 6(a). Both the current gain and the unilateral power gain decreased slightly with the increasing thickness of Si₃N₄ sidewall. It can be explained that at increasing sidewall thickness from 2 nm to 10 nm, sidewall induced access resistance led to increased transconductance degradation, which overran the parasitic capacitance reduction from 2.2 fF/μm, 1.8 fF/μm, 1.6 fF/μm, and 1.4 fF/μm to 1.3 fF/μm, as shown in Figure 6(b).

Figure 5: characteristics of InGaAs MOSFET with sidewall “spacer 1” thickness variation from 2 nm to 10 nm.

(a)

(b)

Figure 6: (a) Current gain, unilateral power gain versus frequency (solid: current gain ; open: unilateral power gain ), and (b) parasitic capacitances and versus frequency (solid: ; open: ) of InGaAs MOSFET with sidewall “spacer 1” thickness variation from 2 nm to 10 nm.

The same thickness variation study was carried out on sidewall “spacer 2,” as shown in Figure 7, where the black curve represents the device with spacer 2 of 2 nm, the red curve represents the device with spacer 2 of 4 nm, the green curve represents the device with spacer 2 of 6 nm, the blue curve represents the device with spacer 2 of 8 nm, and the pink curve represents the device with spacer 2 of 10 nm. It is observed that, for “spacer 2,” the Si₃N₄ sidewall thickness barely affected the drain leakage current, since the extended InP layer prevented the sidewall induced access resistances from increasing. As shown in shown in Figure 8(a), the current gain and the unilateral power gain increased with the recessed sidewall thickness, which was mainly due to the parasitic capacitance reduction from 2 fF/μm to 1.5 fF/μm with constant transfer characteristics, shown in Figure 8(b).

Figure 7: characteristics of InGaAs MOSFET with sidewall “spacer 2” thickness variation from 2 nm to 10 nm design.

(a)

(b)

Figure 8: (a) Current gain, unilateral power gain versus frequency (solid: current gain ; open: unilateral power gain ), and (b) parasitic capacitances and versus frequency (solid: ; open: ) of InGaAs MOSFET with sidewall “spacer 2” thickness variation from 2 nm to 10 nm design.

4. Proposed Device Processing

The proposed sidewall structures show promising electric characteristics according to the device simulation. The InGaAs MOSFET structures without Si₃N₄ sidewall, with Si₃N₄ sidewall “spacer 1,” and with Si₃N₄ sidewall “spacer 2” can be fabricated using the main processing steps shown in Figure 9, which is compatible with normal device fabrication. The epitaxial layers were prepared by Molecular Beam Epitaxy (MBE) that consists of InP substrate, InAlAs buffer layer, InGaAs channel, and InP cap layer from the bottom to the top. Dummy gate using negative resist HSQ was patterned at first to define the gate length (step (1)); then, highly n⁺ doped InGaAs source/drain regrowth was carried out using Metal Organic Chemical Vapor Deposition (MOCVD) (step (2)). After that, HSQ was removed. For “spacer 1” structure, InP cap layer was etched right after HSQ (step (3b)), while InP cap layer was kept for “spacer 2” structure (step (3c)). The etching selectivity between InP and InGaAs can be well controlled by using HCl based chemical solution, as shown in Figure 10, where an illustrative InP pattern was fabricated on the InGaAs surface by perfect wet etching. Si₃N₄ was then deposited using Plasma Enhanced Chemical Vapor Deposition (PECVD) and etched using Reactive Ion Etching (RIE) to form the sidewall along the S/D for both structures (steps (4b) and (4c)). An experimental Si₃N₄ sidewall is obtained using this technique, as shown in Figure 11, where a vertical Si₃N₄ can be observed along the InGaAs side. After that, high- gate oxide was realized using Atomic Layer Deposition (ALD) after (NH₄)₂S surface treatment for “spacer 1” structure (step (5b)), while high- was deposited after InP cap etching for “spacer 2” structure (step (5c)). Gate metal was then carried out followed by source/drain metal patterning. Similar device processing can be found in papers [24, 25].

Figure 9: Proposed device fabrication steps for “spacer 1” and “spacer 2” structures (steps (1) and (2) are the common processing steps, steps (3b), (4b), and (5b) are the “spacer 1” processing steps, and steps (3c), (4c), and (5c) are the “spacer 2” processing steps).

Figure 10: SEM image of selective InP etching on InGaAs surface.

Figure 11: SEM image of Si₃N₄ sidewall realized along the InGaAs side.

5. Conclusion

In this paper, a novel Si₃N₄ sidewall structure was introduced to the regrown source/drain based InGaAs MOSFET technology. By relieving the electric field at gate edge towards the drain side, the new sidewall structures can reduce the drain leakage current to achieve low standby power consumption. It is also able to improve the potential frequency performance by reducing the parasitic source/drain capacitance. Different Si₃N₄ sidewall structures including a normal sidewall and a “recessed” sidewall with extended InP layer were studied with varied Si₃N₄ sidewall thickness. The normal sidewall structure can effectively reduce the drain leakage current but may incur increased access resistance, compromising the frequency performance. As a compensation for this side effect, the novel “recessed” sidewall structure with extended InP layer plays a role in reducing the parasitic capacitance without sacrificing the on-state performance, which can further boost the frequency performance with the Si₃N₄ thickness increase.

Competing Interests

The authors declare that there is no conflict of interests regarding the publication of this paper.

Acknowledgments

This work is supported by the National Natural Science Foundation of China (Grant no. 61604128) and the Fundamental Research Funds for the Central Universities (Grant no. 2016QNA4025).

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