Modeling and Simulation of Ultra-Wideband Communication Receiver Based on Balanced Sampling and Integrating Circuit

In order to solve the problem of extracting signals from impulse radio ultra-wideband (IR-UWB) receivers in a low signal-to-noise ratio (SNR) environment, this paper uses circuit transient analysis to establish a mathematical model of an ultra-wideband wireless communication receiver based on a balanced sampling and integration circuit (BSIC). e eect of receiver circuit component parameters on the output signal is simulated and tested, and the optimization of circuit component parameters for UWB wireless communication receivers is achieved. e sampling capacitance in the receiver circuit ranges from 1 pF to 6 pF, depending on the 200 ps pulse width. e output signal amplitude increases as the sampling capacitance increases. e range of integral capacitance is from 2.5 pF to 25 pF, which is based on a 100 ns interval between two pulses. e output signal amplitude decreases as the integration capacitance increases and the signal waveform becomes better as the integration capacitance increases. e eect of SNR from 0 to −30 dB on the receiver output is simulated, and the results show that the Bit Error Ratio (BER) of the receiver is less than 10−3 when the SNR is greater than −15 dB. e simulation and test results show that the model developed in this paper is useful as a guide for optimizing the receiver parameters at low SNR.


Introduction
Impulse radio ultra-wideband (IR-UWB) has high application value in the Internet of ings (IoT) and wireless communications [1][2][3], and IR-UWB technology has been widely used in short-range communications, positioning, and radars [4,5].
Receiver is the basis for the realization of IR-UWB technology. At present, there are many types of IR-UWB signal receiver. In [6][7][8][9], there are incoherent energy detection receivers for the additive Gaussian white noise channel environment and matched lter receivers for correlated reception. In [10,11], there are RAKE receivers consisting of multiple parallel correlators for complex multipath channel environments and transmission reference (TR) receivers [12][13][14][15], which do not require complex channel estimation compared to RAKE receivers. In [16][17][18][19][20][21], the structure of the low-noise ampli er (LAN) is optimized to improve the gain of the LAN and reduce the noise so as to improve the data speed of the receiver and reduce the bit error rate (BER). In [22][23][24][25], the algorithm of analog-to-digital converter (ADC) is optimized to reduce the bit error rate of the receiver. ese improvements can e ectively reduce the BER of UWB receiver, and the data speed can reach 100 Mbps to 1 Gbps. And in [10,12,13,20,24], the e ect of the environment on UWB receivers has been studied. However, most of these studies are carried out in high signal-to-noise ratio (SNR) environment, which has poor antinoise ability. e balanced sampling and integration circuit (BSIC) [26] is a simple and low-complexity circuit for recovering rapidly changing weak signals that are drowning in noise. e di erence between this receiver and other receivers is the di erent position of the ampli er. In other receivers, the received signal is rst processed by LNA and then by energy detection or correlator. In contrast, sampling and integration receivers process the received signal before ampli cation by an ampli er, which reduces the ampli er requirements.
In order to enhance the anti-interference ability of UWB receiver, the circuit in [26] is improved by adding two resistors, so it is necessary to establish a new model of the receiving circuit.
is article mainly adopts the circuit transient analysis method to establish the mathematical model of the UWB wireless communication receiver and obtain the receiver output signal expression through Laplace transform. e influence of receiver circuit component parameters on the output signal is studied, and the circuit component parameters of IR-UWB wireless communication receiver are optimized. e influence of different SNR on the output signal of receiver is studied by simulation. e paper is structured in the following sections: Section 2 establishes the receiver model. Section 3 introduces simulation and measurement methods. Section 4 presents and discusses simulation and measured results. Section 5 describes the summary and future work of this article.

IR-UWB Receiver Modeling
In this section, an IR-UWB wireless communication receiver using a BSIC to achieve correlation calculations between sampling pulses and received signals is studied. e IR-UWB receiver block diagram is shown in Figure 1. e receiver consists of two parts, the signal receiving module and the signal processing module. e signal receiving module consists of an antenna, a BSIC, and an IR-UWB signal generation circuit. e signal processing module consists of an amplifier circuit, a level conversion circuit and a CPLD. Signal capture and decoding are performed on the CPLD. e BSIC in IR-UWB wireless communication receiver is shown in Figure 2, which is composed of three parts: a sampling circuit, an integration circuit, and a high-pass filter circuit. e circuit in Figure 2 is an improvement on [26]. Resistors R 2 and R 3 in Figure 2 have been added to increase the anti-interference capability of the circuit. e sampling circuit is composed of sampling capacitors C 1 , C 2 , diodes D 1 , D 2 , and resistance R 1 , and the sampling pulse is U p . e exponential integrating circuit is composed of integrating capacitors C 3 , C 4 and resistors R 4 , R 5 . e high-pass filter circuit is composed of filter capacitors C 5 , C 6 and resistors R 6 , R 7 . e input signal of the IR-UWB wireless communication receiver is the signal received by the antenna. Diode conduction is controlled by sampling pulse, and input signal is sampled by the sampling capacitor.
e sampling values are integrated by capacitors C 3 and C 4 after the diodes are cut off. e low-frequency part of the integrated signal is filtered out by capacitors C 5 and C 6 , and the signal is input to the differential amplifier. After multiple sampling periods, the output signal of the IR-UWB wireless communication receiver can be obtained.

Circuit Model of Sampling Process of IR-UWB Communication Receiver.
According to the two different working states of IR-UWB communication receiver, the sampling process and the integration process, the mathematical models of the two working stages are established in one signal period. e sampling process is the process in which IR-UWB wireless communication receiving circuit samples the input signal after the sampling pulse conducting the diodes D 1 and D 2 . e resistors R 1 , R 2 , and R 3 are connected in parallel with an equivalent resistance of R q when the diode is conducting. e circuit in the sampling process is shown in Figure 3. And ignore the effect of conduction diode resistors, because the resistors value of diode conduction is much smaller than R 1 , R 2 , and R 3 .
R q in the figure is

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Since the upper and lower parts of the BSIC have the same circuit principles, this article only elaborates on the derivation process of the upper part of the circuit model.
In the nth period, the initial states of C 1 , C 3 , and C 5 are assumed to be u n1 , u n3 , and u n5 , respectively, when the diode is conduction. According to Kirchhoff's voltage law, the simplified circuit model from Figure 3 is shown below.
Because the frequency of the received UWB signal is on the order of GB, the parameters of the upper part of the circuit in Figure 3 satisfy R 6 ≫ R 4 ≫ R q , [R 4 + (R 6 + 1/jωC 5 )//1/jωC 3 ] ≫ R q , and R 6 + 1/jωC 5 ≫ 1/jωC 3 . So i C 1 ≫ i C 3 ≫ i C 5 ; then, the system of equations (2) can be simplified to Perform Laplace transform on the system of equations (3), and perform inverse Laplace transform on the equations to get u 1 (t), u 3 (t), and u 5 (t) as follows: As shown in Figure 3, the upper part and the lower part of the BSIC are symmetrical. Assume that the initial states of the capacitors C 2 , C 4 , and C 6 during diode conduction are u n2 , u n4 , and u n6 , respectively. Similarly, the solutions of u 2 (t), u 4 (t), and u 6 (t) can be obtained as follows:

Sampling circuit
Integral circuit Filter circuit Replace the sampling capacitor

Replace the integral capacitor
Replace the filter capacitor Figure 5: Circuit simulation and measurement principle block diagram.

Circuit Model of Integration Process of IR-UWB Communication Receiver.
At the interval between two sampling pulses, diodes D 1 and D 2 are cut off, and the input signal of the receiving circuit sampled by the sampling capacitors C 1 and C 2 is transferred to the integrating capacitors C 3 and C 4 . After multiple sampling cycles, the integration process of the input signal of the receiving circuit is completed, and the low-frequency part of the signal is filtered out by the highpass filter circuit. e equivalent circuit diagram is shown in Figure 4. When the diode is cut off in the nth cycle, the initial states of the capacitors C 1 , C 3 , and C 5 in the upper half of the circuit are u n1 ′ , u n3 ′ , and u n5 ′ , respectively. e equations can be obtained from the equivalent circuit diagram in Figure 4.
For i C 3 ≫ i C 5 , therefore, C 5 du 5 /dt in the first two equations can be ignored. So, the solution of the equation system can be simplified to e result of the inverse Laplace transforms of the simplified u 1 (t), u 3 (t), and u 5 (t) can be obtained as follows: As shown in the equivalent circuit diagram of the integration process of the receiving circuit in Figure 3, the upper and lower parts of the circuit are symmetrical during the integration process of the BSIC. In the same way, suppose the initial states of the capacitors C 2 , C 4 , and C 6 are u n2 ′ , u n4 ′ , and u n6 ′ , respectively, and the results of u 2 (t), u 4 (t), and u 6 (t) can be obtained as where β � ������������������� Mobile Information Systems In the process of circuit model calculation, the received UWB signal is iterated through equations (8) and (9), according to the initial states u n1 , u n3 , and u n5 of the three capacitors in the upper part of the circuit during diode conduction, and the final state values of u n1 ′ , u n3 ′ , and u n5 ′ of the capacitors C 1 , C 3 , and C 5 in the circuit sampling process  are obtained. u n1 ′ , u n3 ′ , and u n5 ′ are the initial state values of capacitors C 1 , C 3 , and C 5 in the circuit integration process at diode cutoff. rough the iterative operation of equations (8), the final state values of the three capacitors in the upper half of the nth cycle circuit can be obtained. u (n+1)1 , u (n+1)3 , and u (n+1)5 are the initial states of the three capacitors during diode conduction in the next period. e output signal of the upper part of the BSIC can be obtained by iterative calculation with the above method. In the same way, the output signal of the lower half of the BSIC can be obtained. e BSIC is connected to the differential amplifier, and u 2 − u 3 − u 5 + u 6 is taken as the output result of the whole circuit.

Simulation and Test Methods.
In this paper, the mathematical model of equation (10) BSIC is simulated, and the output signal of the actual circuit is measured to study the influence of circuit element parameters on the output signal so as to determine the parameters. e schematic block diagram of circuit parameter simulation and measurement is shown in Figure 5.
As shown in Figure 5, a modulated received signal is generated, and the received signal is input into a receiving circuit that has replaced different capacitance values. e capacitance values of the sampling capacitor, the integrating capacitor, and the high-pass filter capacitor in the circuit have been replaced, respectively. e influence of sampling capacitance, integrating capacitance and high-pass filter capacitance on the output signal of receiver, is studied through the waveform of output signal of receiving circuit. e measured receiving circuit is shown in Figure 6. In Figure 6, on the front side of the receiver (Figure 6(a)) are the BSIC and the amplification circuit. On the back of the receiver (Figure 6(b)) is the IR-UWB signal generation circuit. e BSIC, shown in Figure 5, is above the first black  Mobile Information Systems package amplifier in Figure 6(a). And ports 1 and 8 are 12 V and −12 V power supply. Port 2 is the output of differential amplifier. Port 3 is the output of comparator. Port 4 is the output of amplifier. Ports 5 and 6 connected to ground. Port 7 is the input signal, which controls the sampling switch. Ports 9 and 10 are connected to IR-UWB symmetrical dipole antennas. e measured principle block diagram of the output signal of IR-UWB wireless communication receiver is shown in Figure 7, which is mainly composed of a transmitter, a     As shown in Figures 7 and 8, the encoded signal generated by the encoder is modulated and then emitted by the transmitter, and the signal reaches the receiver through the wireless channel. At the same time, the transmitter sends the synchronous signal to the receiver through the synchronous line. Power supply for UWB wireless communication transmitter and receiver by DC stabilized power supply. e oscilloscope tests the output signal of receiver and the encoded signal of transmitter in different channels. e mathematical model of the receiver proposed in this paper is verified by measuring the output signal of the receiver, which has replaced the values of sampling capacitance, integrating capacitance and high-pass filter capacitance in the receiver.
When the parameters of the receiver are determined, a channel simulation module is added between the modulation signal and the receiver to simulate the channel noise, and the noise category is Gaussian white noise. e SNR is changed during simulation to test the receiver's antinoise ability.

Simulation and Test Setup.
e single narrow pulse signal received by the receiver in the simulation is an ultrawideband signal with a narrow pulse width of 200 ps. e normalized waveform is shown in Figure 9. e signal in Figure 9 is obtained from a Gaussian second-order derivative by simulation of the antenna model in the CST software. e OOK modulated binary code is used in the simulation, the narrow pulse repetition period is 50 ns, and the unit code length is 25 μs. e resistance R 1 is 51 Ω, R 2 and R 3 are 1 MΩ, R 4 and R 5 are 10 kΩ, R 6 R6 and R 7 are 200 kΩ, the capacitors C 1 and C 2 are 4 pF, C 3 and C 4 are 25 nF, and C 5 , C 6 are 19.5 nF. e narrow pulse signal transmitted by the transmitter during the test is shown in Figure 10, and the pulse width is about 250 ps. e OOK modulated binary code is used in the simulation, the narrow pulse repetition period is about 52 ns, and the unit code length is 25 μs. e resistance R 1 is 51 Ω, R 2 and (c)

Receiver Output Signal with Different Sampling
Capacitors.
e value of the sampling capacitor depends on the pulse width of the received UWB signal. e approximate value range of the sampling capacitor can be calculated by the principle of capacitor charging.
where u r + is the receive voltage, u C 1 is the voltage of sampling capacitor, and R q C 1 is the time constant τ. For the UWB signal pulse width is 200 ps, τ can be 50 ps, 100 ps, 200 ps, and 300 ps. e corresponding sampling capacitors C 1 and C 2 are, respectively, 1 pF, 2 pF, 4 pF, and 6 pF; the output signal of the receiving circuit can be obtained through the simulation of (10) as shown in Figure 11. e relationship between the value of sampling capacitance C 1 , C 2 and the output waveform amplitude obtained by simulation of the receiving circuit through equation (10) is shown in Figure 12.

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It can be clearly seen from Figures 11 and 12 that when the sampling capacitance C 1 and C 2 is changed, the output waveform amplitude of the BSIC changes significantly. e output signal of the receiving circuit increases with the increase of the sampling capacitance. When the sampling capacitance is 6 pF, the output signal amplitude of the receiving circuit decreases slightly.
When the sampling capacitors C 1 and C 2 are, respectively, 1 pF, 2 pF, and 4 pF, the output signal waveform of the BSIC is shown in Figure 13. e influence of different sampling capacitors on the output signal amplitude of the BSIC is shown in Table 1.
As shown in Figure 13 and Table 1, the amplitude of the output signal of the BSIC increases with the increase of the sampling capacitance, and the trend is the same as the simulation result, when the sampling capacitance does not exceed 8 pF.

Receiver Output Signal with Different Integral
Capacitance.
e value of the integrating capacitor is determined by the interval between two narrow pulses. e charging process of the integrating capacitor C 3 is the same as the discharge process of the sampling capacitor C 1 . e discharge time constant for the sampling capacitor is as follows: Because the interval between two narrow pulses is 100 ns, the integrating capacitors C 3 and C 4 are 2.5 nF, 5 nF, 25 nF, and 50 nF, respectively, the output signal of the receiving circuit can be obtained through the simulation of (10), as shown in Figure 14. Figure 15 shows the relationship between the integrating capacitors C 3 , C 4 and the receiving circuit through the simulation of equation (10).  As shown in Figures 14 and 15, the amplitude of the output signal of the receiving circuit decreases as the integral capacitance C 3 and C 4 increase. When the integrating capacitance increases to 5 nF, the output signal amplitude of the receiving circuit decreases rapidly. When the integrating capacitance increases from 5 nF to 50 nF, the output signal amplitude of the receiving circuit decreases gradually.
When the integrating capacitors C 3 and C 4 are, respectively, 22pF, 4.7 nF, and 22 nF, the output signal waveform of the BSIC is shown in Figure 16. e influence of different integrating capacitors on the output signal amplitude of the BSIC is shown in Table 2.
As shown in Figure 16 and Table 2, when the integrating capacitor is 22 pF, there is no obvious waveform amplitude as a DC voltage. When the integrating capacitor is 4.7 nF, part of the waveform amplitude can be seen to be 648 mV. When the integrating capacitor is 22 nF, obvious waveforms can be seen, with an amplitude of 640 mV. e simulated and measured results are the same in that the output waveform becomes better when the integrating capacitor is around 22 nF. e difference is in the output waveform when the integration capacitance is less than 22 nF.

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Receiver Output Signal with Different Filter Capacitance.
When the filter capacitors C 5 and C 6 are, respectively, 9.75 nF, 19.5 nF, 39 nF, and 78 nF, the output signal of the receiving circuit obtained by the simulation based on equation (10) is shown in Figure 17. e amplitude relationship between different filter capacitors C 5 , C 6 and the output signal of the receiving circuit simulated through equation (10) is shown in Figure 18.
It can be seen from Figures 17 and 18 that the amplitude of the output signal of the receiving circuit increases with the increase of the filter capacitors C 5 and C 6 .
When the filter capacitors C 5 and C 6 are 10 nF, 18 nF, and 39 nF, respectively, the output signal waveform of the BSIC is shown in Figure 19.
e influence of different high-pass filter capacitors on the output signal amplitude of the BSIC is shown in Table 3.
As shown in Figure 19 and Table 3, the output signal amplitude of the BSIC increases with the increase of the high-pass filter capacitor value, but the waveform is obviously distorted when the waveform reaches 39 nF. e measured result trend is the same as the model simulation result.

Simulation Results of Received Signals under Different SNR.
When SNR is −30 dB, the time-domain waveform diagram of the received signal and the receiver output signal is shown in Figure 20.
To show the differences between all receiver output signals, the receiver output SNR and BER of receiver output signal is provided in Figure 21. e input SNR is the ratio of signal to noise in the channel. e output SNR is the ratio of the receiver output signal to the output noise. e BER is obtained by dividing the number of error bits by the total number of bits transmitted. e number of erroneous bits is obtained by statistical method. e receiver output SNR decreases as the SNR decreases in Figure 21, and the BER also increases as the SNR decreases. Figure 21 shows that the BER of the receiver output signal is less than 10-3 when the input SNR is greater than −15 dB.  e antinoise performance of the receivers in this paper is compared with other receivers in Table 4. e operating environment, BER, and pulse width of the receivers are compared in Table 4. It can be seen from the table that the UWB signal pulse width used in this paper is the narrowest. When BER is the highest, it is in the same order of magnitude as other receivers, but its corresponding SNR is the lowest, which is −30 dB. e receiver proposed in this paper is 1 to 4 orders of magnitude lower than other receivers at the minimum BER, and its corresponding SNR is also the lowest. is indicates that the receiver's antinoise ability is stronger than other receivers operating in high SNR environments.

Discussion
rough the simulation and measured results in Sections 4.1 to 4.3, it can be seen that the BSIC model established in this paper is consistent with the real circuit. However, in order to simplify the calculation, some parameters in the model are  is work Ref. [10] Ref. [12] Ref. [13] Ref. [22] Ref. [ ignored, which leads to a little difference between the calculated results using the model and the measured results. In Section 4.4, the simulation results of the model in different SNR environments are compared with the results of some articles. e comparison results show that the antiinterference ability of BSIC receiver is stronger than other compared receivers. However, due to the characteristics of capacitor charging and discharging, the upper limit of data rate of BSIC receiver is lower than receivers with other structures. erefore, the BSIC receiver can be mainly used in areas with relatively bad channel environment.

Conclusions
e IR-UWB receiver based on BSIC is improved to enhance its anti-interference ability. e mathematical model of the improved BSIC is established by using the circuit transient analysis method, and the expression of the output signal of the UWB wireless communication receiver is obtained by Laplace transform. e receiver parameters are studied and optimized based on BSIC model. e results of the study show that the integration capacitance in the receiver circuit has the greatest impact on the received signal waveform at an interval of 100 ns with a width of 200 ps; the smaller the integration capacitance, the worse the received signal waveform, in the range of 2.5 pF to 25 pF. is is basically the same as the test results. Simulation and test results show that the receiver model developed in this paper can serve as a guide for optimizing the receiver circuit parameters. e effect of noise on the output signal of the receiver was investigated and compared, and the results showed that the BER of the receiver is less than 0.005 when the SNR is greater than −15 dB. e comparison results show that the antiinterference ability of the improved BSIC receiver is stronger than that of other receivers. is improvement is effective. e next step is to increase the data transmission rate of this receiver.

Data Availability
e data used to support the findings of this study are included within the article.