This paper introduces a new scheme to achieve a dynamic logic gate which can be adjusted flexibly to obtain different logic functions by adjusting specific parameters of a dynamical system. Based on graphical tools and the threshold mechanism, the distribution of different logic gates is studied, and a transformation method between different logics is given. Analyzing the performance of the dynamical system in the presence of noise, we discover that it is resistant to system noise. Moreover, we find some part of the system can be considered as a leaky integrator which has been already widely applied in engineering. Finally, we provide a proof-of-principle hardware implementation of the proposed scheme to illustrate its effectiveness. With the proposed scheme in hand, it is convenient to build the flexible, robust, and general purpose computing devices such as various network coding routers, communication encoders or decoders, and reconfigurable computer chips.
For years, the construction of integrated circuits has required a vast amount of time and money for combining different logic gates. In 1985, when the first field-programmable gate array (FPGA) was introduced to the world, the era of reusable “field-programming” began which led to a more flexible implementation of integrated circuits. However, the speed of an FPGA reconfigurable scheme is typically slow, since it needs some time for “rewiring” [
In 1998, a novel way of configuring dynamic logic gates was introduced by Sinha and Ditto [
In this work, we propose a scheme to obtain dynamic logic functions by controlling simple dynamical systems. Based on the threshold mechanism, we give a transformation method between different logics and analyze its antinoise and time-delay characteristics. We find that the scheme is robust to system noise. Furthermore, the main part of the system can be designed based on the leaky integrator which has been applied into different research fields, such as in neuronal or cell analysis and filters related to signal processing. Finally, the scheme is proved to be effective by simulation results of a logic gate circuit.
We now propose a new method to change the function of a logic gate flexibly by altering only one parameter or two specific parameters. The formula of its implementation is
When system (
Based on the threshold mechanism introduced by Murali et al. [
To implement the dynamic logics, the most significant step is to set
Typically, we consider that a logic gate has two inputs and one output, for example, we suppose that
The relationship between the inputs and the output.
For arbitrary
Input 0 | 0 | 0 | 1 | 1 |
Input 1 | 0 | 1 | 0 | 1 |
Output | 0 |
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For
Input 0 | 0 | 0 | 1 | 1 |
Input 1 | 0 | 1 | 0 | 1 |
Output | 0 |
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Figure
(Color online) the judging method of the system output, where the navy blue, green, red, and baby blue lines represent the situations of inputs
Figures
By a similar analytical method, all the logic gates can be achieved by the proposed scheme as summarized in Table
All available logic gates for the system.
Region |
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Logic gate |
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I |
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1 |
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OR | ||
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1 | ||
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1 | ||
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1 | ||
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NAND | ||
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1 | ||
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II |
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1 |
|
OR | ||
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XNOR | ||
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NAND | ||
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1 | ||
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III |
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1 |
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OR | ||
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AND | ||
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XNOR | ||
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NOR | ||
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NAND | ||
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1 | ||
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IV |
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1 |
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OR | ||
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AND | ||
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0 | ||
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NOR | ||
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NAND | ||
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1 |
In reality, noise is unavoidable. Generally, there are two types of noise: input noise and system noise. Figure
(Color online) the influences of input and system noises on the performance of the system, where (a) in a noiseless case; (b) in the presence of input noise whose range is
When the system is added with system noise, then
Figures
The parameter
The system block diagram of a leaky integrator.
Note that
(Color online) the evolution of
The physical implementation of a logic cell is an important step for successful applications [
(Color online) the circuit diagram of the system (
In Figure
By (
(Color online) simulation results of an OR gate.
Similar results can be achieved as the frequencies of the inputs increases. When the frequencies of the inputs become large enough, the lag time must be taken into consideration. As discussed above, the increment of
The proposed method can be used to other systems such as fractional oscillators [
To sum up, a scheme to realize a dynamic logic gate is introduced in this paper. Based on the proposed scheme, all available logics and its transformation method are discussed. Besides, the noise and lag characteristics of the system are studied. We find that the system is resistant to system noise and its response time can be easily controlled. Finally, a circuit implementation for an OR logic gate is provided as an example. Other feasible logic gates can be achieved similarly. The scheme is both straightforward and robust which enables a strong flexible hardware implementation with very low cost. This dynamic logic gate can be applied as a universal basic hardware element to build various kinds of communication encoders and decoders, network coding routers, specific reconfigurable computer chips, graphics processor units, reconfigurable multimedia video cards, or specific systems that require frequent transformations between different logics. Moreover, there are some further significant directions to be investigated such as all kinds of reconfigurable network coding routers and reconfigurable cyclic code encoder or decoder based on the proposed reconfigurable dynamic logic gate. Communication and computer hardware devices based on such dynamic logic scheme may be more flexible and robust than the existing statically wired hardware.
The authors would like to thank the reviewers for their helpful advices. This paper is supported in part by the AoE grant E-02/08 from the University Grants Committee of the Hong Kong Special Administration Region, China, the Hong Kong Scholars Program (Grant no. HJ2012005), the China Postdoctoral Science Foundation Funded Project (Grant no. 2012T50209), the National Natural Science Foundation of China (Grant nos. 61070209, 61100204, 61272402), the Beijing Higher Education Young Elite Teacher Project, the Shenzhen Municipal Key Laboratory of Key Technology and Application (Grant no. C.02.12.00301) and the Fundamental Research Funding of Shenzhen, China (Grant no. C.02.13.00701).