Designing All-Pole Filters for High-Frequency Phase-Locked Loops

. Since the phase-locked loop (PLL) circuit was proposed in the 1930s, it is being used for a lot of situations when precise frequency and phase references are required. Among these applications, synchronous telecommunication networks experienced a strong development in order to support the explosive information traffic that the modern society demands. Consequently, bandwidth became a decisive parameter, implying higher and higher frequencies for the clock signals exchanged between the nodes of the networks and detected by PLLs. The necessity to improve clock precision that follows the bandwidth increase provoked the improvement of the filter component of the PLLs, avoiding instability and high-frequency components in the reference signals. Here, a technique of designing this kind of filter is presented, considering second-order filters, implying third-order PLLs. Simulations show that following this technique produces very fast tracking processes, enabling precise operation even for very high frequencies.


Introduction
Phase-locked loop (PLL) was conceived by de Bellescize in 1932 [1] and has been used to generate frequency and phase signals for several types of applications such as demodulation, digital signal transmission, and clock recovering in synchronous networks.In the last thirty years, digital electronics revolution produced high speed integrated service networks based on master-slave time distribution systems with very precise central clocks sending signals to slave nodes that, by using cheap and precise PLLs, reconstruct the necessary time basis [2].
Along this time, the implementation of circuits to execute the PLL functions evolved from analog to digital circuits and even software PLLs are now used in engineering applications [1], including synchronous communication networks.
Considering telecommunication services, a first view could indicate that multiplier phase detectors have been replaced by digital phase and frequency detectors with charge pump [3].In spite of this, due to bandwidth requirements, the development of optical clock detectors is based on multiplier phase detection and they are very useful in high speed networks [4][5][6].
Consequently, the double-frequency jitter, which is less critical in the digital versions of phase and frequency detectors, becomes more significant with the development of high speed optical networks and master oscillation drifts spoil the synchronous state reachability [7,9].To solve this problem, one can use high-order filters in the PLL, increasing the order of the whole loop, but providing adequate high-frequency operation.
Here, some design strategies for PLL filters are proposed, in order to avoid double-frequency jitter effects, decreasing considerably acquisition times and allowing good synchronism performance for network nodes built with PLLs.
The filters to be chosen are all-pole for which there are results about how to avoid bifurcations and undesired oscillations [10].The idea is to present different filter options to implement PLLs with free-running frequencies of hundreds of GHz.
In Section 2, some general PLL principles are discussed in a very brief way, emphasizing the liner approximation and the transfer functions of the filter and of the whole loop.Section 3 is about the root locus peculiarities of the PLL all-pole transfer functions with order greater than 2. In Section 4, the designing method is presented with Section 5 showing some examples to illustrate the robustness and generality of the procedure.Section 6 shows and compares results between the presented methodology and the usual light-wave technology validating the described procedure and showing its improvements.Section 7 presents some concluding remarks.

General PLL Principles
The main PLL function is to generate an output signal V  () having phase   () that is related to phase   of an input signal V  () so that the difference   () −   () maintains a constant value as time passes; that is, the signals V  () and V  () reach the same frequency [1].
As shown in Figure 1, PLLs are composed of three fundamental blocks: a phase detector (PD), a linear low-pass filter , and a voltage controlled oscillator (VCO).The PD compares the phase of the input signal V  () with the phase of the VCO output signal V  (), in order to achieve a constant phase error as described above.Filter () is supposed to eliminate high-frequency components generated by the PD operation.Filter () also has the function of defining the PLL dynamics [11].
When a PLL is used for clock extraction, the input signal comes from the transmission medium, which may be pairs of copper wires, microwave radio links, or optical fibers.This input signal contains a component characterized by the frequency of the clock used in the generation of the transmission signal.
The other components of the input signal interact in the PD with the signal V  () and a large portion of these components are eliminated by the action of the loop filter.A small fraction of these components, with small effective power, will fall within the filter passing band and their effect will be perceived as noise in the PLL dynamics [1,11].
Consequently, clock extraction operation can be described as the synchronization of the VCO with the clock frequency component from the input signal.Thus, in Figure 1, the input signal V  () and the VCO output signal V  () are supposed to be periodic and given by In high-frequency PLL implementations, object of this work, the PD is commonly a signal multiplier with a multiplying factor denoted by   [4,5].Considering, additionally, that the filter eliminates the double-frequency terms, the error signal V  is with   =     /2, called detection gain and measured in volt/rad.Here, the lock-in mode is considered and, consequently, the PLL is operating around the synchronous state and the right side of (2) can be written considering small phase errors; that is, sin(  () −   ()) =   () −   () [7].
Finally, as the VCO phase is controlled by with  V being called VCO constant and measured in rad/s⋅V, the transfer function for the whole linear PLL is as follows: In PLL jargon,  =  V   is called loop gain and is measured in s −1 [1].This parameter is important to calculate the synchronization range of the linear PLL, that is, the maximum angular frequency difference between V  () and V  () for a synchronous state to be reachable.Calling |Δ| the modulus of this angular frequency difference, synchronization is possible if [10,11] To give an idea of the meaning of (6), in typical optical communication systems, a 20 Gbits/s system with a tolerance of 10 ppm for the clock signal is considered.Under these conditions, the necessary loop gain to extract the clock needs to be greater than 1.256⋅10 6 s −1 .As a consequence of this high gain, the filter needs to be carefully designed, in order to combine synchronization conditions and stability.

All-Pole PLLs with Order Greater Than 2: Root Locus Properties
As shown in the last section, the whole loop PLL transfer function given by ( 5) has an all-pole form, with the following properties: (i) the branches of the root locus of () start at the zeros of ().In particular, one of the branches starts at the origin, which is one of the poles of () [13]; (ii) the branch of the root locus of () starting at the origin always enters the left half plane [10]; (iii) all branches of the root locus of (), as  → ∞, tend to infinity along asymptotes inclined relative to the real axis by angles of /(+1), 3/(+1), 5/(+1), . . .[13]; (iv) pairs of symmetrical root locus branches that go to infinity along asymptotes not coincident with the real axis and forming angles of magnitude less than /2 with the real axis create pairs of imaginary poles when crossing the imaginary axis.In general, the crossings of different pairs of branches occur at different values of .The values of  at each crossing will be the solutions of the equation Δ −1 () = 0, where Δ −1 is the ( − 1)-th Hurwitz minor of the polynomial () +  [10]; (v) the onset of instability will happen at gain   , corresponding to the first crossing of the imaginary axis in the root locus of () + ; (vi) all root locus branches that cross the imaginary axis never come back [10].This property only holds if the zeros of () are all located in the left half-plane; (vii) the consequence of the last property is that the crossings of the imaginary axis will always occur two at a time, corresponding to the conjugate complex roots contained in symmetrical branches of the root locus.
Considering these properties, root locus of transfer functions given by ( 5) has the general appearance shown in Figure 2, which exemplifies the root locus of normalized PLLs, that is, with a 3 dB gain at angular frequency 1 rad/s.Figure 2(a) presents a 6th-order Bessel filter [14,15] in the loop and Figure 2(b) presents a 4th-Butterworth filter [14,15] in the loop.As can be seen, it is possible to characterize the onset of As a practical consequence of these properties, PLLs present a range of positive values of , such that, for all values in that range, all poles of transfer function () of ( 5) are located in the left side of the complex plane, implying that the system is stable.Another consequence is that a stability threshold may be defined for any system described by this transfer function.
This stability threshold   is defined as the value of the gain  for which the first pair of root locus branches crosses the imaginary axis.Thus, all PLL systems described by a transfer function (5), operating with  <   , are stable.
There are other additional considerations to choose , but only values lesser than   must be used.Determination of stability threshold   is discussed in the Appendix, where some algorithms are presented.As a matter of illustration, Table 1 shows values of   for some normalized standard filter types, considering () order.

Design Method
In this section, a new method for designing filters for PLLs is presented.The method is based on the definition of a standard form for the transfer function [14,15] for the loop filter.The procedure is divided into two stages: gain calculation and denormalization of the transfer function.

Defining the Transfer Function Gain.
As the permitted VCO gain range is defined, as shown in the former section, the next step is to choose a value for this parameter.In order to do this, some objectives must be conciliated.
The first is to obtain a PLL able to operate with high gains in optical digital communication systems [8] and also capable of operating in face of the phenomenon so-called "jitter." A second point is that PLL transfer functions () amplify frequency variations in the input phase signal if there are overshoots in the frequency response of |()| 2 , or, in other words, if there are angular frequencies  such that |()| 2 > 1.
Consequently, |()| 2 showing overshoots must be avoided.Calling () the denominator polynomial of (), one of the ways to attain this objective is to impose |()| 2 monotonically increasing.
By using an analogous reasoning to the "maximally flat at  = 0" approach used in the Butterworth approximation [14,15], in the ideal situation, all coefficients of powers of  different from 2 + 2 and 0 must be zero, in order to vanish the derivatives of |()| 2 up to the order 2 + 1 at  = 0.This is not possible, since several coefficients of |()| 2 do not depend on .But, since the main objective is to have |()| 2 with monotonically increasing behavior and, in the normalized case, only the angular frequencies of the first order are responsible to characterize the pass-band, the stability condition can be guaranteed.
Therefore, the most significant nonconstant term in |()| 2 is related to  2 , since the next term corresponds to  4 , being smaller or of the same order of magnitude as  2 .If the parameter  is reduced, the coefficient of the  2 term is ( 2 0 − 2 1  0 ) for all loop filter transfer functions with orders equal to or greater than 2, increasing up to reach  2 0 for  = 0.This coefficient of  2 passes through zero when  is given by If   is further decreased up to a value smaller than   , 10 to 20% reductions are enough to have |()| 2 monotonically increasing and therefore free of overshoots.When   is greater than   , 50% reductions in the value given by (7) imply that |()| 2 is monotonically increasing and therefore free of overshoots.

Denormalizing the Transfer Function.
Suppose that the aim is to obtain a PLL transfer function () following an all-pole filter transfer function.Since all standard filter types have transfer functions expressed in normalized form, that is, transfer functions with 3 dB frequency equal to 1, then the normalized coefficient  0 and the normalized denominator (  ) are known, where   is the normalized complex variable.
Following this procedure, one can precisely define the PLL transfer function (), with the transfer function () of the loop filter being automatically defined by ().
The expression for the normalized PLL loop transfer function (  ) is given by where  + 1 is the order of the PLL.The normalized loop gain   =   0 /  1 and the normalized coefficients    , . . .,   0 are assumed to be determined by the chosen type of filter [12,[14][15][16].
In order to implement the desired transfer function () and the loop filter transfer function (), it is necessary to denormalize (  ) given by ( 8) by using the appropriate angular frequency   that plays an important role in defining loop gain .Additionally, designing all-pole filter [12,16] requires the definition of the group delay function (), evaluated at  = 0, or simply (0).
As shown in [12,16], the group delay at   = 0, corresponding to a normalized transfer function given by ( 8), is as follows: The denormalized PLL transfer function () has the same form as (8) but with coefficients  −1 , . . .,  1 and loop gain .Thus, the group delay function at  = 0 corresponding to the () should be given by the same form as ( 9), but with  replacing   ; that is, Besides, for a normalized low-pass frequency transformation, the normalized group delay   (  ) and the group delay (), as shown in [12], are related by and, consequently: Thus, since   , calculated by the procedure defined in Section 4.1, is determined by coefficients   0 and   1 , in order to obtain a PLL transfer function with a given , the standard filter must be denormalized to a frequency   , by using (12).Then, the substitution   = /  in (5) results in the PLL transfer function:  with   being the quotient between the 3 dB angular frequency of the chosen standard filter and the 3 dB angular frequency of the normalized transfer function.

Application Examples
Here, the described procedure is applied to three types of PLL all-pole filters: a 5th-order Butterworth, a 5th-order Chebyshev, and an arbitrary 3rd-order filter.For each case, the PLL frequency response and the capture performance are presented, showing that the developed design procedure allows very fast signal tracking.The results were obtained by simulations with MATLAB [17] and considering the linear PLL model with phase error belonging to the interval [−, ] [18].
Simulation results are shown in Figure 3: PLL frequency response (Figure 3(a)) and capture performance (Figure 3(b)).It can be observed that the 3 dB bandwidth is about half of the sum frequency of the input signal with the VCO center frequency and tracking time is about 10 s.
In this case, the reference loop gain   resulted in a PLL frequency response free of overshoots, without the need of reducing this value.
In this case, the reference loop gain   was corrected to 80% of the value determined by (7), resulting in a PLL frequency response with 0.077 dB overshoot.
Simulation results are shown in Figure 5: PLL frequency response (Figure 5(a)) and capture performance (Figure 5(b)).It can be observed that the 3 dB bandwidth is less than half of the sum frequency of the input signal with the VCO center frequency and the tracking time is about 11 s.
In this case, the reference loop gain   was corrected to 89% of the value determined by (7), resulting in a PLL frequency response with 0.011 dB overshoot.
The examples have shown that, despite the different structures presented for the filters, the tracking time is almost the same in the analyzed cases.Consequently, it could be conjectured that the tracking time performance depends only on a good choice for the gain.

Designing for Light-Wave Technology
In order to show comparisons between the methodology developed here and results presented for synchronization concerning light-wave networks, the reference work presented in [5] will be discussed.There, the authors describe an  filter used in the PLL, shown in Figure 6, with a transfer function given by with  0 = 1/ and  1 = 3/.
Results obtained in [5] show the loop behavior for loop gains ranging from 500 Hz to 1 MHz and undesirable selfsustained oscillations appear around 1 MHz gain.
For the situation with loop gain  = 1.885 ⋅ 10 6 (rad/s)/V, considering the calculated   , the corresponding denormalized  is 1.9491 (rad/s)/V, well above the value of   = 0.1667 (rad/s)/V and near   = 3 (rad/s)/V.This proximity suggests that the PLL with this loop filter and with  = 1.885⋅10 6 (rad/s)/V is still stable, but with damped oscillatory behavior during input phase transients.This behavior is observed in the capture process shown in Figure 7, obtained in a simulation with a loop filter with the same  and  values as used in [5] and with  = 1.885 ⋅ 10   presented in [5], it can be concluded that they are the same, validating the design and simulation procedures followed here.
Additionally, these procedures can be applied as an improvement to the design presented in [5], taking the same PLL  filter and considering a loop gain corresponding to 1 MHz as, in this case, the PLL proposed in [5] fails to capture the synchronous state.
The denormalization factor is   = 37.692 ⋅ 10 6 , considerably higher than that presented in [5].Consequently,  = 2.653 ⋅ 10 −8 s that is feasible with  = 22Ω and  = 1.21 nF.Simulation results are shown in Figure 8: PLL frequency response (Figure 8(a)) and capture performance (Figure 8(b)).It can be observed that the tracking time has order of magnitude equal to 1.5 s.

Conclusions
Methods for the implementation of PLL with order greater than 2 were presented, providing the possibility of adjustment of loop gain  for arbitrary large values.The obtained PLLs are stable with a relatively large margin of robustness.
It was shown that, starting with normalized forms of the loop transfer functions, parameters defining the limits of instability for the PLLs can be calculated, permitting one to obtain transfer functions free of or with acceptable overshoots.
The procedure has shown that the loop filters to be used in PLLs may be scaled to permit the use of arbitrarily high loop gains.
With the availability of wide-band operational amplifiers, with gain-bandwidth products greater than 100 MHz, it can be anticipated that there are no serious limitations to the practical implementation of PLLs with the filter types discussed here.
Such PLLs could be useful in the implementation of clock recovery in large speed optical communication systems, as well as in other digital high speed systems.

Appendix
Algorithm for the Calculus of   for  = 2 to 5. Using some properties from the theory of equations and considering the expression of () as described in this work,

Figure 2 :
Figure 2: Root locus for all-pole PLL transfer functions: examples.

Figure 7 :
Figure 7: PLL capture with the  filter.

Table 1 :
Stability threshold for standard filters.
instability for a transfer function according to (5) by the value of   of the loop gain.Such a value of loop gain is associated with a pair of imaginary poles of transfer function.