H ∞ LPV Control with Pole Placement Constraints for Synchronous Buck Converters with Piecewise-Constant Loads

This paper addresses the output regulation problem of synchronous buck converters with piecewise-constant load fluctuations via linear parameter varying (LPV) control scheme. To this end, an output-error state-space model is first derived in the form of LPV systems so that it can involve amismatch error that temporally arises from the process of generating a feedforward control.Then, to attenuate the mismatch error in parallel with improving the transient behavior of the converter, this paper proposes an LMI-based stabilization condition capable of achieving both H ∞ and pole-placement objectives. Finally, the simulation and experimental results are provided to show the validity of our approach.


Introduction
Drawing on the development of electronic technology, switching DC-DC converters have been widely and successfully applied to a variety of power conversion systems such as DC power supplies, DC motor drivers, and power generation systems (see [1][2][3][4] and the references therein).Recently, with the growing interest in linear matrix inequalities (LMIs) [5], some advanced control techniques have been investigated regarding to output regulation of DC-DC buck (step-down) converters that produce a lower output voltage than the input voltage, especially for T-S fuzzy control [2,[6][7][8][9][10].Indeed, the asynchronous buck converters operating in a largesignal domain are generally modeled in terms of nonlinear systems.Thus, based on the T-S fuzzy model derived from the averaging method for one-time-scale discontinuous systems (AM-OTS-DS), [9] has successfully designed an integral T-S fuzzy control with respect to the output regulation problem of the asynchronous buck converter.Meanwhile, in the case of synchronous buck converters [11][12][13], the use of the low-side FET plays an important role in eliminating the voltage drop across the power diode of the nonsynchronous converter, which allows buck converters to be modeled with linear timevarying systems.
In general, the operation of the DC-DC converter is usually affected by the fluctuation of output loads [3,9,12,13].For this reason, it is of great importance to consider the presence of a wide load range in the problem of regulating the output voltage and current levels of DC-DC converters; that is, it has become a hot topic to maintain high efficiency in a great load fluctuation.Moreover, due to the fact that conventional pulse-width modulation (PWM) buck converters have poor efficiency under light load [14], numerous research efforts have been invested to improve the efficiency of the PWM converters with a wide load range (see [12,[15][16][17] and the references therein).However, a remarkable point is that most of references cited above have paid considerable attention at the hardware level to cover such problem.Further, [13] used a reduced system model with the limits in theoretically capturing the dynamic behavior of piecewise-constant load fluctuation in the process of implementing the robust periodic eigenvalue assignment algorithm [18].In other words, limited work has been found in terms of the control theory.Motivated by the concern, this paper proposes a suitable approach in light of the control theory to take the effect of load fluctuations into account.
This paper addresses the output regulation problem of synchronous buck converters with piecewise-constant load fluctuations.To consider the presence of such load fluctuations, we derive an output-error state-space model in the form of linear parameter varying (LPV) systems [19][20][21], thereby converting the underlying regulation problem into the stabilization problem.Here, it is worth noticing that a mismatch error that temporally arises from the process of generating a feedforward control is clearly incorporated into the LPV model and it is attenuated by the H ∞synthesis technique [22,23].However, H ∞ design provides little control over the transient behavior [24,25].Hence, to attenuate the mismatch error in parallel with improving the transient behavior of the converter, this paper proposes an LMI-based stabilization condition capable of achieving both H ∞ and pole-placement objectives.Finally, the simulation and experimental results are provided to show the validity of our approach.
Notation.The notations  ≥  and  >  mean that  −  is positive semidefinite and positive definite, respectively.In symmetric block matrices, ( * ) is used as an ellipsis for terms induced by symmetry.For any square matrix Q,

Modeling for DC to DC PWM Buck Converter
The equivalent circuit for a class of synchronous DC-DC buck converters and the corresponding closed-loop control system are depicted in Figure 1, where the following notations are used.
(i)  DS denotes the static drain to source resistances of the high-side and low-side power MOSFETs, respectively.
(ii) V  () and V  () denote the power input and output voltages, respectively, where it is assumed that V  () = V  is time-invariant.
(iii)   () and V  () denote the inductor current and the capacitor voltage, respectively.
(iv)  and  denote the inductance and capacitance selected by the given design specifications including the switching frequency of MOSFETs.
(v)  DCR and  ESR denote the equivalent series resistances of the inductor and capacitor.
(vi) () and () denote the piecewise-constant load resistance subject to  − ≤ () ≤  + and the duty ratio of PWM buck converter.
Then, based on averaging method for one-time-scale discontinuous system (AM-OTS-DS) [26], the mathematical model of the buck converter under consideration is described as follows: Further, combining (2) and (3) yields by which ( 1) and ( 2) can be rewritten as follows: Let V  be a unique equilibrium point of V  () and assume that the value of () is piecewise-constant; that is, () =   for  ∈ T  (see Figure 1).Then, by (6), the equilibrium point of   (), that is,   , is given by Further, by (3), the equilibrium point of V  () is given by V  = V  .Hence, from (1), the equilibrium point of (), that is, , is given by Remark 1.This paper focuses on addressing the case where the variation of () is subject to a class of switching signals whose finite intervals T  are larger than the setting time.
Remark 2. Indeed, it is extremely hard to directly measure the value of V  () in the considered buck converter owing to the existence of  ESR (see Figure 1).Thus, to find the value of V  () from the ones of the measured V  (),   (), and   (), we introduce a method of using the following equality derived from (4): Remark 3. From ( 9), we can see that Mathematical Problems in Engineering Remark 4. To solve the regulation problem herein, we need to find the desired value of   = V  /  from (7), where V  is a prescribed value and   can be established as follows: Then, for  ∈ T  , the system given in ( 5) and ( 6) can be converted into

LPV Control with Pole Placement Constraints
Proposition 5. Let us consider the feedforward control input () of the following form: where () ∈ L 2+ denotes the error that can temporally occur when finding   and  , under the saturation operator (10).Here, a remarkable point is that if () = 0, then the feedforward control input () =  for  ∈ T  .
In order to address the D-stability problem, we consider the following theorem reported in [24], which will be used for the design of LPV control with pole placement constraints.
Remark 8.In general, when investigating the output regulation problem of synchronous buck converters, we need to consider the dynamic behavior of some natural phenomena such as piecewise-constant load fluctuations and mismatch errors arising when generating the feedforward control.Thus, based on the framework of LPV control theory, this paper makes an attempt to impose such natural phenomena in the control design.

Simulation and Experimental Results
The parameters of the considered buck converter (1)-( 3) are listed in Table 1.As shown in Table 1, the equilibrium point of V  () is given by V  = 5, and the lower and upper bounds of () are given by  − = 3 and  + = 20, which leads to  1,0 = 0.9662,  1,1 = 0.9948,  2,0 = 0.0.0497, and  2,1 = 0.0.3221 from (17).As a result, system (15) can be represented as follows: For three LMI regions {D  } =1,2,3 , Theorem 6 provides the corresponding control gains and the minimized H ∞ performances for (37), which are listed in Table 2. Figure 2 shows the behaviors of the output voltage V  (), simulated by MATLAB (dot-line) and PSIM (solid-line), for the control gains corresponding to the LMI region D 2 .Here, to verify the effectiveness of the proposed approach, we consider the piecewise-constant load   that changes from 5 Ω to 10 Ω (see Figure 2    Next, an experiment is additionally carried out to confirm the applicability of our approach verified through the simulation results.The parameters used herein are set the same as the ones listed in Table 1, and a dual N-channel MOSFET (FDS8949) and two current sense amplifiers (LMP8481) are used for the hardware implementation.Here, we need to tackle several problems concerning the measurement of the required output signals to construct the controller.First of all, the ringing problem arising from the used MOSFET should be addressed (1) by changing the Q-point factor that influences the setting time of V  ; and (2) by adding the RC snubber circuit placed between the low-side MOSFET and inductor.In what follows, the residual switching noises should be attenuated to exactly measure the values of   (),   (), and V  () with respect to the common ground.To do so, the power voltage V  is thoroughly isolated from the applied voltage used for the operation of sensor units, which plays an important role in reducing such switching noises in the side of the sensor units.Finally, it is necessary to eliminate the undesirable effects of electromagnetic interference (EMI) that may be caused by the wrong PCB layout.In this sense, all net paths on the PCB board are designed as short as possible, and the top and bottom layers of the PCB board without inner layers are not assigned to draw the power and ground nets.Figure 3(a) shows the construction of our experimental bench, which consists of a prototype of buck converter (see Figure 3(b)), a dSPACE board, an oscilloscope, and an electronic loader.Here, data acquisition and real-time control system are implemented on the basis of dSPACE 1104 software and digital processor card, which have useful functions such as analog/digital converters (ADCs) and pulse-width modulation (PWM) built in TMS320F240 DSP. Figure 4(a) shows the output response V  () of the buck converter with   changing from 5 Ω to 10 Ω, from which we can observe that the maximum overshoot of V  () is approximately 180 mV and its setting time is less than 1.5 ms.In addition, Figure 4(b) shows the output response V  () of the buck converter with   changing back to 5 Ω, which illustrates that the maximum undershoot of V  () is approximately 180 mV and its setting time is less than 1.5 ms.That is, by making a comparison between Figures 2 and 4, we can see that this experiment achieves similar output transition performances to the ones of the simulation results, which means that our approach can be practically applied to the output regulation problem of synchronous buck converters with load fluctuations.

Concluding Remarks
In this paper, we have shed some light on addressing the output regulation problem of synchronous buck converters with piecewise-constant load fluctuations via linear parameter varying (LPV) control scheme.Thus, based on the derived LPV model, an H ∞ stabilization condition is proposed such that (1) the mismatch error arising temporally in the feedforward control term can be attenuated and (2) the closed-loop poles can lie in the a prescribed LMI region.Finally, the validity of the proposed approach is verified through the simulation and experimental results.

Figure 1 :
Figure 1: Equivalent circuit for a class of synchronous DC-DC buck converters and piecewise-constant load fluctuations.
(a)) and back to 5 Ω (see Figure 2(b)), where T 2 = 0.0025 s is set for simulation.From Figure

Figure 3 :Figure 4 :
Figure 3: (a) Experimental bench for testing the proposed approach and (b) experimental prototype of synchronous DC/DC buck converter.
Moreover, the control gains   can be reconstructed by   =    −1 .Proof.
(15)t can be found that the transient responses obtained from MATLAB and PSIM simulations are approximately equal in view of the average mode, which means that the obtained LPV model(15)is valuable in investigating the regulation problem of synchronous buck converters.In particular, from the PSIM simulation result, we can see that the proposed control offers the short setting time 1 ms (less than T 2 as mentioned in Remark 1), small overshoot 180 mV, and nearly zero steady state error even though there exist piecewise-constant load fluctuations in the synchronous buck converter.

Table 2 :
H ∞ performance and control gains for each LMI region.