Unified Approach for Robust Stability Analysis of Buck Converters with Discrete-Time Sliding Mode Control

'is paper proposes a novel discrete-time sliding mode (DTSM) control approach to address the robust stability problem of buck converters with multiple disturbances.'e contributions lie in the “unified” modelling and controller design. In modelling, all the possible model uncertainties and external disturbances are considered and further classified into two cases. It can also be extended to the situations with individual/several disturbances. While for the controller design, differing from the traditional DTSM based on the nominal model, the disturbances are directly introduced in the process, giving the robust stability condition and four new regulation subranges. It is suitable for both nominal and perturbed systems. Finally, the influences of the sampling time and disturbances on the control performance are investigated. Simulations and experiments confirm the benefits of the unified approach with greater accuracy and wider applications.


Introduction
e issue of model uncertainty and external disturbance is widespread and challenging for the control of power converters. It might be related to the internal circuit elements, input power supply, measurement device, external environment interference, and so on [1][2][3]. For example, in [4], the magnetic characteristics of inductor are proved to vary greatly in presence of large magnetic flux density; in [5], the variations of load resistor and input voltage are proved not to be neglected, especially in case of large signal operation.
As a kind of favourite DC/DC power converters, buck converters have been widely used in renewable energy systems, distributed generation systems, marine power plants, and so on [6,7]. ey are characterized as nonlinear and time-varying systems with model uncertainties and external disturbances. In modelling, many efforts have been centred on diverse kinds of system descriptions and auxiliary observers [8][9][10][11][12]. In [1], the commonly used average statespace model is given. In [13], the disturbances of load resistor, inductor, and capacitor are considered and a unified linear fractional model with structured dynamic uncertainties is proposed. In [11], a stochastic system model is proposed for buck converters with noise and load disturbance. In [12], a Hammerstein model is proposed for the case of duty-cycle disturbance. However, at present, many researchers only focus on one or several disturbing factors in practical applications. Although as an alternative solution auxiliary observers are generally adopted to relieve the burden of high-precision modelling [9,14,15], it increases the system complexity and can still not cover all the possible model uncertainties and external disturbances.
For the control of buck converters, the pulse width modulation (PWM) is a conventional approach but suffers from the bottleneck of model precision, especially when facing the possible disturbances [1,9,13,16]. As an effective robust control substitute, sliding mode (SM) control technology has been widely adopted with advantages of implementation simplicity, guaranteed stability, and fast response [1,2,[17][18][19][20]. A survey of recent SM applications in power converters can be referred to [1,20]. e current research mainly focuses on designing the resistant-disturbance controllers and compensators. For the former, it is often used to overcome some kinds of matching disturbances directly [2,17,19]; while for the latter, it is generally used for some specific mismatching disturbances [21][22][23], which can not satisfy the matching condition of SM [1,2,[21][22][23]. However, due to the diversity and complexity of model uncertainties and external disturbances of converters, whether there is a unified approach for the design and analysis of SM controllers is an interesting problem worthy of consideration but has been barely investigated.
With the rapid development of programmed microprocessor chips, the discretization is another issue not to be avoided for SM controlled converters [24][25][26]. In general, the discretization realization includes two steps: designing an appropriate control algorithm in continuous-time domain [1,17] and further making an analogue-to-digital transformation for the corresponding digital controller [27][28][29]. In order to guarantee the stability of discrete-time sliding mode (DTSM) control systems, the sampling time and controller parameter are proved to be the two key factors [24,[29][30][31][32]. For the former, the smaller the sampling time is, more closely the DTSM system approximates to the original continuous-time counterpart. However, it increases the hardware costs and computational burdens. For the latter, due to the inherent switching nonlinearity of SM control, how to regulate the controller parameters is still an unsettled problem. In [24,[28][29][30], it has proved that inappropriate discretization can aggravate the control performance, leading to low accuracy and high wear of physical parts, even to the point of causing instability.
Based on the above analysis, a unified approach is proposed to address the robust stability problem of DTSM controlled buck converters with multiple disturbances. How to regulate the controller parameter and sampling time? What are the disturbances that affect the quality of the output voltage? ey are two key questions. As a result, a unified approach of modelling and design of DTSM controller is proposed. To be specific, the contributions of this paper can be concluded as follows: (1) all possible model uncertainties and external disturbances of buck converters are considered in modelling and control, including the variations of input and reference output voltage, parameter uncertainties of load resistor, inductor, and capacitor, and time-varying external disturbances; (2) differing from the traditional DTSM approach [1,24,27,31], four more accurate subranges of controller parameter can be achieved by the stability analysis; and (3) the influences of the sampling time and disturbances on the controller regulation and control performance are investigated simultaneously. e structure of this paper is organized as follows. In Section 2, the system description of SM controlled buck converter under multiple disturbances is given, following the unified disturbance analysis and discretization of the system. In Section 3, a unified approach of DTSM controller is proposed by the robust stability analysis, following the influences of the sampling time and disturbances on the system. e simulations and experiments are presented in Section 4 and concluded in Section 5 to validate the proposed approach with greater accuracy and wider applications.
Notations. e following notations are used throughout this paper. T denotes the transpose of the matrix, I∈R n denotes the n × n identity matrix, O(.) denotes the infinitesimal term of the corresponding parameter, and the items with "Δ" represent the disturbances of the corresponding nominal variables. Figure 1 gives the system diagram of a SM controlled DC/ DC buck converter [1,17,19]. In the converter circuit, E is the input DC voltage source; L, C, and R are the inductor, capacitor, and load resistor; i L and i C are the currents flowing through L and C, respectively; v c is the output voltage; D is a diode; S w is a power switch; V ref is the DC reference voltage of v c ; the states x 1 and x 2 are defined as the output voltage error and its derivative as follows:

System Description
To realize the ON/OFF control of the power switch S w , this paper directly adopts the inherent switching characteristics of SM control as follows [1,2]: which is implemented by the hysteresis circuit [1,19]; u � 1 and u � 0 are used to denote the status of switch ON and OFF, respectively; s is the SM variable designed later.

Modelling the Buck Converter under Disturbances.
Here, we assume that the buck converter works in continuous conduction mode. Based on the average state-space modelling approach and Kirchhoff's circuit law, the ON/ OFF operations of the buck converter in Figure 1 can be described, respectively, as By combining (3) and (4), it yields In this paper, we consider all the possible model uncertainties and external disturbances. erefore, (5) can be changed as where the items with "Δ" are the corresponding disturbances of the nominal variables R, E, L, and C and d 1 (t) and d 2 (t) are the external disturbances, and their time derivatives are assumed bounded.
Here, we define ΔV ref as the variation of the reference output voltage V ref . By combining (1), (6) can be further changed as where the terms ω 1 (t) and ω 2 (t) are denoted as , Rewrite (8) in the form of state space as follows: where the state x � [x 1 , x 2 ] T and the nominal matrix A, B, and D are listed as and ∆B, ∆D 1 , ∆D 2 (t), and ∆D 3 (x) represent the lumped input disturbance, constant disturbance, time-varying disturbance, and state disturbance deduced as where ω 2 0 � 1/LC. Observed from (11), these lumped disturbances are caused by different disturbing factors, i.e., the circuit parameter vibrations such as ∆E, ∆C, and ∆L and the external . And all the model uncertainties and external disturbances of buck converters are included. As mentioned above, much literature only considers one or several disturbances [10][11][12][13]. It is also the reason that diverse models have been established.

Analysis of the Multiple Lumped Disturbances.
In the following, a unified modelling approach is proposed to cover all the possible disturbances as well as the possible situations with individual/several disturbances. erefore, two cases are discussed. (9), it contains all the model uncertainties and external disturbances. Here, we rewrite it as

Case 1. For
where , and d 2 (t) located in (9) are considered separately. Based on the modelling approach in (1) and Kirchhoff's circuit law, the corresponding average state-space models can be similarly deduced and summarized in Table 1, where ζ i (x, t) is the possible combination of the corresponding constant disturbance, state disturbance, and time-varying disturbance. e disturbance matrices ΔB j , ΔD 1i , and ΔD 2j , i � 1, 2, j � 1, 2, 3, are deduced as By combining (12) and Table 1, here we further classify them into two cases. Because of coupling with the input control u, it is obvious that the input disturbance ∆B j could hinder the controller design so that is categorized separately where j � 1, 2, 3 while the others are classified into a group. erefore, the two unified expressions in Table 1 can cover all the possible situations of buck converters with the individual or several or all disturbances in practice.

Discretization of the Buck Converter
System. In the following, we adopt the zero-order holder (ZOH) to realize the discretization of the buck converter system [24,25,27]. To cover the two unified expressions in Table 1, we take the worst situation with all the disturbances in (12) to discuss the system discretization.
By adopting ZOH, the state value can be held constant during the sampling period h until the next moment arrives.
erefore, the continuous model (12) is changed into a sampled-data system as where Φ and Γ are denoted as where I ∈ R 2 and O(h 3 ) is the item with orders higher than h 3 but ignored in this paper. Furthermore, for (14), the time-varying disturbance [∆D 2 (k + 1)h − τ] and input disturbance ΓΔBu(k) hinder the design of DTSM controller later. erefore, they are needed to be dealt separately. For the former, based on the first integral mean value theorem [33], the time-varying dis- where ξ∈[kh, (k + 1)h]. While for the latter, the coupling of input disturbance ΔB and the control u(k) still exist after discretization. Fortunately, due to the superiority of the direct ON/OFF control in Figure 1, the ZOH discretization of u in (2) can be expressed as where s k � sgn[s(k)]. And if the power switch S w is OFF, there is u(k) � 0 and ΓΔBu(k) � 0 while on the contrary, it has u(k) � 1 and ΓΔBu(k) � ΓΔB. Here, we take the worst case to cover the impact of the input disturbance ΔB, i.e., replacing the disturbance term ΓΔBu(k) in (14) by ΓΔB.
By combining (14), (17), and (18), the discretization of the continuous model (12) can be finally obtained as Observed from (11), since the first rows of the matrix ΔB, ΔD 1 , ΔD 2 (ξ), and ΔD 3 (x) are all zero, we define It is worth noticing that the discrete model in (19) corresponds to the worse situation with all the disturbances in (12). From Table 1, the difference of the two unified models of buck converters lies in the term ∆B j u, j � 1, 2, 3. erefore, the discrete models of the two unified expressions can be similarly deduced as where ξ∈[kh, (k + 1)h] is the same as (17) and ζ i (x, ξ) corresponds to the discretization of the disturbances ζ i (x,t), i � 1, 2.
From (13), since ζ i (x, ξ) represents the combination of the possible constant disturbance, state disturbance, and time-varying disturbance, they can be further denoted as d 3i (x, ξ) as (20), where i � 1, 2. In essence, the two discrete models in (21) can be concluded into a unified expression as (19) despite of different disturbing terms, which depends on the contained disturbances in practice. It also proves the effectiveness of the two unified expressions in Table 1, which can cover all the possible situations of buck converters with the individual or several or all disturbances in practice.

Robust Stability of DTSM Controlled Buck Converters
In the following, a unified DTSM control approach is proposed based on the above unified modelling and analysis of the robust stability for buck converters. Still taking the worse situation with all the disturbances in (19) as an example, the influences of the sampling time and lumped disturbances on the control system are two key problems need to be addressed.

Design of DTSM Controller.
Due to the advantage of easy implementation, the discrete signals x 1 (k) and x 2 (k) are adopted to design a linear SM surface s(k) for the ON/OFF control of buck converter in Figure 1 as where the design parameter c � [λ, 1], λ > 0. In fact, other types of sliding surfaces such as terminal SM and nonsingular terminal SM [19] can also be used, wherein the sliding variable s(k) can be regarded as a threshold in (18) to trigger the power switch. (19), if the sliding surface s(k) is designed as (22), the control law u(k) is implemented as (18) and the robust stability condition is satisfied with the following inequalities, where l 1 (λ, h) and l 2 (λ, h) are defined to express the corresponding conditions when the power switch is ON and OFF, respectively, as follows:

Theorem 1 (robust stability analysis). For the discrete model of buck converter in
en, the whole closed-loop DTSM control system can be guaranteed stable.
Proof. In this paper, differing from the traditional DTSM approach based on the nominal model [1,24,27,31], since all the possible model uncertainties and external disturbances in (19) are included into the controller design, the existing condition of DTSM should be satisfied [24,[29][30][31][32], i.e., which is equivalent to |s(k + 1)| < |s(k)|. By substituting (18) into (19), the whole closed-loop DTSM control system can be obtained as where the total lumped disturbance v(k) is denoted as From (15) and (16), s(k + 1) can be further obtained from (22) as where the variables ψ(k) and Θ can be deduced as Based on the existing condition of DTSM in (24), two cases in accordance with the power switch ON/OFF need to be discussed in the following: (1) If s(k) > 0, then u(k) � 0 can be obtained from (18).
And the existing condition of DTSM in (24) is equivalent to s(k + 1) < s(k) for the case s(k + 1) > 0 and s(k + 1) > s(k) for the other case s(k + 1) < 0. However, as the system converges to the equilibrium point in the phase plane (x 1 , x 2 ), i.e., ((x 1 (k) � 0, x 2 (k) � 0)), it is easy to prove that the condition s(k) s(k + 1) < 0 will make the system run across the sliding line s(k) � 0 and cannot be guaranteed to always hold [34]. erefore, from (27)- (29), the guaranteed robust stability condition can be obtained as (2) If s(k) < 0, similarly s(k + 1) > s(k), u(k) � 1 holds and the stability condition is deduced as Furthermore, by substituting (15), (16), and (20) into (30) and (31), the robust stability condition in cases of power switch ON and OFF can be changed as For the items c(Ah + A 2 h 2 /2) and c(hI + Ah 2 /2) in (32), they can be further denoted from (10) as erefore, by substituting (33) and (34) into (32), the robust stability condition (23) can be finally achieved. □

Influence of the Sampling Time on Controller Regulation.
From the guaranteed stability condition in eorem 1 and (23), it is known that the control performance of the system is determined by the sampling time h, lumped disturbance d 3 (x, ξ), and DTSM parameter λ simultaneously. In the following, we first investigate the relationship of the sampling time h and DTSM parameter λ in the phase plane (x 1 , x 2 ).
Theorem 2 (relationship of the sampling time and DTSM parameter). In order to guarantee the robust stability of DTSM controlled buck converter system in (25), the parameter λ is recommended to be chosen within the four subranges: (1) 0 < λ < ψ 1 ; (2) ψ 1 < λ < ψ 2 ; (3) ψ 2 < λ < ψ 3 ; and (4) λ > ψ 3 , where Proof. Based on the guaranteed stability condition in (23), the slopes of the lines l 1 (λ, h) and l 2 (λ, h) are the same and denoted as For the comparative study imposed by the lumped disturbance d 3 (x, ξ), the stability condition of the nominal counterpart of (19) can also be deduced as where l 1 ′ (λ, h) and l 1 ′ (λ, h) are defined to express the corresponding conditions when the power switch is ON and OFF, respectively. It is worth noticing that their slopes are as the same as ρ(λ, h) in (36).
Here, we define two variables h 1 (λ) and h 2 (λ) as which are the two critical values of the denominator and numerator, which determine the sign of the slope ρ(λ, h) in (36). According to the ON/OFF operation of the power switch, as well as the two critical variables h 1 (λ) and h 2 (λ) in (38), the robust stability conditions of the DTSM controlled buck converter system with/without disturbances, i.e., (23) and (37) are illustrated and compared in Figures 2(a)-2(c), where these regions are mutually intersected by the sliding line s(k) � 0 and the lines l 1 (λ, h) and l 2 (λ, h). e four regions are defined as follows: Region I (l 1 (λ, h) > 0, s(k) < 0, and u � 1); Region II(l 2 (λ, h) < 0, s(k) > 0, and u � 0); Region III (l 1 ′ (λ, h), s(k) < 0, and u � 1); and Region IV (l 2 ′ (λ, h) < 0, s(k) > 0, and u � 0). It should be noted that the lines l 1 (λ, h) and l 2 (λ, h) may not be straight lines due to the existence of the time-varying disturbance d 3 (x, ξ). In phase plane (x 1 , x 2 ), four cases will be discussed in the following.   ρ(λ, h) is negative. erefore, the slope ρ(λ, h) > 0, and the robust stability regions are illustrated in Figure 2(c). And the DTSM parameter λ is recommended as Case 4. ρ(λ, h) < 0: Still let the variable h 1 (λ) < 0 as Case 3 based on the condition (λ − 1/RC) < 0. In order to make the other variable h < h 2 (λ), ρ(λ, h) < 0 should be held so that the robust stability regions can be described as the same as Figure 2(a). Correspondingly, the DTSM parameter λ is recommended as Based on the robust stability analysis of the above four cases, the relationship of the sampling time h and DTSM parameter λ can be determined. And accordingly, the three critical values of λ can be finally obtained as (35). □ Remark 1. Differing from the traditional DTSM based on the nominal model [1,24,27,31], the disturbances are directly introduced in the controller design, giving four new subranges, shown in Figure 3. It is more accurate and timesaving.

Remark 2.
For the recommended choice of DTSM parameter λ in (35), in essence it is deduced from ρ(λ, h) in (36), which is the slope of the lines l 1 (λ, h), l 2 (λ, h), l 1 ′ (λ, h), and l 2 ′ (λ, h) at the same time. In other words, the proposed design approach of DTSM controller in eorem 2 is suitable for both the nominal and perturbed systems. It is also the reason of the so-called "unified" controller design in this paper.

Remark 3.
Considering the limitation of the hardware circuit, special attention should be paid to the subrange 0 < λ < ψ 1 , where the sampling time is restricted with h > 2RC. Meanwhile, it is known that the biggest switch frequency of power switch f s is expected to be less than half of sampling frequency based on the Shannon sampling theorem [35], i.e., f s < 1/4RC. However, considering the switching capability of the physical power switch, e.g., IGBT and MOSFET, if the conditions h > 2RC and f s < 1/4RC cannot be satisfied at the same time, the value of ψ 1 in (35) is of no practical use. In other words, (1) 0 < λ < ψ 2 , (2) ψ 2 < λ < ψ 3 , and (3) λ >ψ 3 can be used to replace the four subranges in eorem 2.

Influence of the Lumped Disturbances on Control
Performance. For the lumped disturbance d 3 (x, ξ) in (19), since it is directly contained in the design of DTSM controller, it does not affect the system stability. Guaranteed by

Region I Region II
Region III Region IV  Figures 2(a)-2(c), it will affect the steady-state error of the system, which can be estimated from the boundary of the robust stability regions. erefore, how the lumped disturbance d 3 (x, ξ) affects the control performance is another important question need to be addressed.

Theorem 3 (influence of the lumped disturbance on the steady-state error). For the DTSM controlled buck converter in (25), if the robust stability condition (23) is satisfied and the DTSM parameter λ is chosen as (35), the output voltage v c varies within [d 3 (x, ξ)/ω 2 0 , E + d 3 (x, ξ)/ω 2 0 ] and the error of its changing rate is d 3 (x, ξ)/(λ − 1/RC).
Proof. For the DTSM controlled buck converter in (25), it can be stabilized under the robust stability condition (23), i.e., after the sliding variable s(k) in (22) is forced to zero, the equilibrium point of the system in phase plane (x 1 , x 2 ) can be calculated as (0, 0). From (1), since the output voltage v c (k) � x 1 (k) − V ref and _ v c (k) � x 2 (k), their steady-state errors can be estimated from the boundary of the robust stability regions in Figures 2(a)-2(c).
In Region I and Region II with lumped disturbances d 3 (x, ξ), the size of the boundary is determined by the four intersection points of l 1 (λ, h) and l 2 (λ, h) with x 1 axis and x 2 axis, i.e., X 1 (k), X 2 (k), Y 1 (k), and Y 2 (k). erefore, we can calculate them from (23) and (36) as While in Region III and Region IV without lumped disturbances (nominal system), the four points of l 1 ′ (λ, h) and l 2 ′ (λ, h) with x 1 axis and x 2 can be obtained from (37) as New proposed approach Traditional approach λ > 0 By comparing the four points X 1 (k) and X 2 (k) in (43) and X 1 ′ 1(k) and X 2 ′ (k) in (44) By comparing (45) and (46), it can be seen that the changing rate of output voltage _ v c (k) is also affected by the lumped disturbance d 3 (x, ξ) and the error of its changing rate can be obtained as d 3

Simulations and Experiments
In order to validate the unified approach of modelling and controller design for the buck converter in Figure 1, its circuit parameters are given as follows: E � 18 V, L � 1000 μH, C � 3200 μF, R � 10 Ω, and V ref � 9 V.

Simulation Results.
Based on the results of eorems 1-3, the proposed unified design approach of the DTSM controller can be concluded as the following two steps: Step 1. Regardless of the buck converter with one or several or the all disturbances in practice, it is recommended to ignore its disturbance temporarily and to choose DTSM parameter λ and sampling time h. In other words, the practical model with disturbance is replaced by its nominal counterpart and further applied (35) to it. Based on the relationship of the sampling time h and DTSM parameter λ in (35), it has ψ 2 � 1/RC � 31.25, and ψ 1 and ψ 3 are determined by the sampling time h. Based on the Shannon sampling theorem [35], the biggest switch frequency of power switch f s is expected to be less than half of sampling frequency, i.e., f s < 1/4RC (78.1 Hz) and the sampling time h is expected with h > 2RC (6.4 ms). Since the switching frequency of the physical IGBT and MOSFET used in power converters is general dozens of kHz, the four subranges in Figure 3 can be replaced by the following three subranges: (1) 0 < λ < 31.25, (2) 31.25 < λ < ψ 3 , and (3) λ > ψ 3 . In this paper, we choose the sampling time h � 1 ms, 0.5 ms, and 0.25 ms for comparisons and then ψ 3 � 189.98, 109.99, and 70.47, respectively. Correspondingly from (35), DTSM parameter λ can be chosen as 15, 60, and 250, respectively. e performance comparisons with different pairs of (h, λ) are shown in Figure 4 and Table 2. In Figure 4, by comparing the output voltages v c labeled from A1 to A9, it can be seen that the control performances of the buck converter are affected by the sampling time h and DTSM parameter λ simultaneously. From Table 2, the nine pairs of (h, λ) are all suitable in practical applications. Especially for A1, A2, and A3 with the same sampling time h � 1 ms, their response time, steady error, and relative steady error of output voltages v c are almost the same, listed as 4 ms, 3.90, and 0.434‰, respectively. It means that the choice of the pair (h, λ) is not unique for the same performance index. Continuously, we compare A4, A5, and A6 with h � 0.5 ms and A7, A8, and A9 with h � 0.25 ms from two aspects. On the one side, if we fix the sampling time h, the bigger the DTSM parameter λ is, the smaller the response time is, while the values of steady error and the relative steady error of the output voltages v c are maintained. It means that the sampling time h is more sensitive to the system than the DTSM parameter λ. erefore, it is recommended to determine the value of h prior to that of λ. On the other side, if we fix the DTSM parameter λ, with the decrease in the sampling time h, the values of the response time will increase inversely, while the values of the steady error and v c will decrease. Since the regulation of the DTSM controller is based on the stability condition in (23), the deduced pair (h, λ) in (35) only affects the static performances (e.g., steady error and relative steady error) but is not directly related to the dynamic performance (e.g., response time), which is listed in Table 2 just for reference.
Step 2: For the bounded lumped disturbance d 3 (x, ξ) in (20), the next is to determine its influences on the system. In order to cover all the possible model uncertainties and external disturbances in (11), here we assume ΔB � [0, 0.0025Esin /RL] T . e reason of choosing the same amplitude 0.0025V ref for ΔD 1 , ΔD 2 (t), and D 3 (x) is only to check whether the parallel shift function imposed by different disturbances is true or not. e sampling time is fixed as h � 0.5 ms, and the DTSM parameter λ is still chosen as 15, 60, and 250, respectively. e simulation results are given in Figure 5 and Table 2, labeled from B1 to B3.
In Figure 5(a) and Table 2, A4, A5, and A6 correspond to the nominal system, while B1, B2, and B3 correspond to the perturbed system. By comparisons, it can be seen that their response times are almost the same and not affected by the lumped disturbance d 3 (x, ξ), but the values of steady error and relative steady error of the output voltages v c increase correspondingly. Furthermore, from the comparisons of local dynamics in Figure 5(b), their steady error changes and the parallel shift function imposed by disturbances are reconfirmed.

Experiment Results.
In order to validate this paper, Figure 6(a) describes the structure of the experiment platform based on DSpace for the buck converter. e Rapid Control Prototype (RCP) system is composed of two parts, i.e., MicroAutoBox is used for collecting the voltage and current of the buck converter and RapidPro outputs the PWM signal for the direct control of the buck converter. Besides, they are linked with interface of Low-Voltage Differential Signaling (LVDS). e software of Matlab/ Simulink is installed in the host PC for developing algorithm following the program compiled by Real-Time Work (RTW) shop and then downloaded in MicroAutoBox. e real-time calculation is in DSpace 1401. e experiment flow diagram of DSAPCE is simplified in Figure 6(b), which is suitable for the algorithm design and performance analysis.
In order to prove the proposed unified approach to be suitable for diverse disturbances, four working modes of buck converters are selected as examples: (1)      from 50 Ω to 100 Ω and then back to 50 Ω; and (4) input voltage changes from 16 V to 25 V and then back to 16 V.
In experiment, the sampling time h is chosen as 0.5 ms. Referring to Table 2, the DTSM parameter λ is chosen as 170. And the contrastive experimental results are given in Figure 7, where the output voltages of the four working modes are marked as D1, D2, D3, and D4, respectively. We can see that the DTSM controller can provide enough robustness to reject these disturbances. Despite the two peak values 8.18 V and 7.75 V for D3 and one peak value 8.54 V for D4, the steady errors of the four cases are listed as 0.32 V, 0.21 V, 0.24 V, and 0.26 V, respectively, which are acceptable in practice. erefore, the experiment results validate the proposed unified approach with wider applications under heavy uncertainty.

Conclusions
In this paper, the robust stability problem of DTSM controlled buck converters is investigated and a unified approach of modelling and controller design is proposed for all the possible model uncertainties and external disturbances. In modelling, two unified expressions are proposed to describe the possible individual/several/all disturbances. In the design of DTSM controller, the disturbances are directly included in the process, instead of ignoring them in the traditional approach. Innovatively, four more accurate subranges arise for the controller regulation. Based on the robust stability analysis, the influences of the sampling time and disturbances on the control system have also been investigated. Simulations and experiments validate the effectiveness and wider applications of the proposed approach.
Data Availability e data used to support the findings of this study are included within the article.

Conflicts of Interest
e authors declare that they have no conflicts of interest regarding the publication of this paper.