Mathematical Problems in Engineering
Volume 2021 (2021), Article ID 9930767, 9 pages
https://doi.org/10.1155/2021/9930767

Research Article

Neutral-Point Potential Balance Control Strategy on Three-Level Active Power Filters

Fei Li, Na Geng, Guifeng Wang, Chunjie Li, Zhan Liu, and Zhenglong Xia

School of Electrical Engineering and Automation, Jiangsu Normal University, Xuzhou 221116, China

Correspondence should be addressed to Na Geng; gengna@126.com

Received 13 March 2021; Revised 7 May 2021; Accepted 2 June 2021; Published 15 June 2021

Academic Editor: Xiao-Shun Zhang

Copyright © 2021 Fei Li et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract.

This paper presents a simplified strategy in neutral-point (NP) potential balance of the neutral-point-clamped (NPC) three-level three-wire active power filter (APF). By introducing a simplified carrier-based pulse width modulation (CB-PWM) strategy and analysing the occurrence mechanism of NP potential unbalance, we proposed a NP potential balancing control strategy based on the simplified strategy. With this strategy, the NP current in a sampling period can be calculated through the detection of compensating current of APF. The three phase’s duration time of reference voltage can also be computed through detecting the voltage fluctuation of upper and lower capacitors accurately, according to the law of charge conservation. Experiment results show that this proposed approach with simplified computation can effectively achieve NP potential balance.

1. Introduction

As the power electronics technology develops fast in recent decades, much attention has been given to the study of power grid optimization [1]. The active power filter (APF) is an important device for harmonic suppression in optimizing power quality, which can compensate the dynamic reactive power and harmonic distortion on the frequency and amplitude in real time [2]. In medium-voltage and high-power applications, multilevel topology has been widely adopted in APF for its numerous advantages, especially the higher DC-bus voltage utilization [3].

The neutral-point-clamped (NPC) three-level converter [4–6] is one of the preferred options in high-power medium-voltage applications for its simple topology and mature control technology. However, the neutral-point (NP) potential unbalance still remains as a major limitation.

Therefore, various modulation strategies have been proposed to solve the problem of NP potential unbalancing in NPC converters. These proposals can be classified into two categories according to their PWM modulation strategies [7]. The first category is space vector PWM (SVPWM) strategy [8–16], including nearest three space vector pulse width modulation (NTSVPWM) and virtual space vector pulse width modulation (VSVPWM). These strategies allocate the duration time of small vector to balance the NP potential. The second category adopts the carrier-based PWM [17–20] which injects zero-sequence voltage in three-phase reference voltage.

The balancing method presented in [13, 14] was based on the opposite effects of a pair of small vectors on neutral-point potential under the SVPWM algorithm. The neutral-point potential is balanced by selecting the positive or negative short vectors in a switching period. Such a method rearranges the time distribution of the short vectors and changes the switching sequence. Thus, the balance of neutral-point voltage is achieved but with prolonged switching transitions due to its complicated and intensive control algorithms.

In [17–20], researchers proposed a strategy that injected zero-sequence voltage in three-phase reference voltage based on carrier-based PWM. However, the NP potential balancing of this strategy requires too complex calculation of zero-sequence voltage. The NP potential control algorithm based on SVPWM was applied in the three-level shunt APF system in [21], which, however, was only simulated in modelling but not verified with experiments.

The present research, aiming to optimize the NP potential balancing, introduces a novel simplified CB-PWM strategy with NP potential balance control to the three-level three-wire APF system. Compared to the traditional CB-PWM, this strategy is more simplified and can significantly reduce the execution time, compensate the harmonic current, and effectively solve the NP potential offset problem. The effectiveness of this novel control strategy is verified with experiments.

2. Simplified CB-PWM Strategy

2.1. Principle of NPC Three-Level Three-Wire APF

A structural schematic diagram of typical NPC three-level three-wire APF is shown in Figure 1. The NPC three-level converter is connected to power grid through a reactor Ls. C₁ and C₂ are DC-bus capacitors of three-level converter, respectively.

Figure 1: Structural schematic diagram of three-level APF.

The control diagram of the three-level three-wire APF system is shown in Figure 2. The system consists of current loop with a PI (proportional integral) regulator, a voltage loop with a PR (proportional resonant) regulator and a NP potential balance controller, and grid voltage and load current detection. Besides, simplified CB-PWM strategy for the NPC three-level converter is adopted to generate PWM signals to drive the NPC converter.

Figure 2: Block diagram of the APF system.

Compared to the traditional converter system, the APF system is more complex because it involves an extra step of harmonic detecting including the low-pass filter and the current controller with the PR regulator. The precision of the compensation will be determined by the execution speed of the algorithm.

2.2. Principle of Simplified CB-PWM Strategy

Structural schematic diagram of NPC three-level APF is shown in Figure 1. Each phase of the converter has three switching states as P, O, and N, signifying that the output terminal voltages are Udc, 0, and −Udc, respectively. Table 1 presents the terminal voltage of each phase and switching states of each bridge.

Table 1: Switching states of the three-level NPC converter (X = A, B, C).

SX1
SX2
SX3
SX4
Terminal voltage
Switching state

ON
ON
OFF
OFF
Udc
P

OFF
ON
ON
OFF
0
O

OFF
OFF
ON
ON
−Udc
N

The reference voltage space vector is then introduced in Figure 3. It can be calculated with the terminal voltage of three phases, Va, Vb, and Vc:

Figure 3: Voltage space vector diagram of the NPC three-level converter.

Figure 3 shows voltage space vector diagram of the NPC three-level converter. There are 27 switching states on the three-level converter, which means it has a much larger quantity of basic vectors than the two-level converter. As to traditional SVPWM schemes, it takes over long time to select sectors (or triangle region) and calculate the space vector duration. The researchers, based on the two aspects above, propose a simplified CB-PWM strategy, which is applied in a three-level three-wire APF system to reduce the amount of computation greatly.

Figure 3 shows that all vectors are divided into 6 sectors. An easier way for selecting sectors in space voltage vectors is proposed, and the principles that it follows is shown in Table 2.

Table 2: Principles of sector selection.

uA_ref
uB_ref
uC_ref
S

>0
<0
<0
1

>0
>0
<0
2

<0
>0
<0
3

<0
>0
>0
4

<0
<0
>0
5

>0
<0
>0
6

uA_ref, uB_ref, and uC_ref are reference voltages of three phases. For example, reference voltage space vector locates in sector I (S = 1), which means uA_ref  > 0, uB_ref  < 0, and uC_ref  < 0, as shown in Figure 4. Reference voltage space vector can be obtained from (including and ), , and .

Figure 4: locating in sector I.

Based on traditional voltage-second balance, it can be expressed that

According to simplified CB-PWM strategy, reference voltages of three phases can be obtained:

Equation (3) and Figure 3 show that when uA_ref  > 0, terminal voltage of phase A uAO consists of Udc and 0 (indicated by state P and O); when uB_ref  < 0, terminal voltage of phase B uBO consists of −Udc and 0 (indicated by state N and O). Similarly, terminal voltage of phase C uCO consists of −Udc and 0 (indicated by state N and O).

Therefore, the phases’ duration time could be obtained as follows:

According to (4), the switching sequence in Sector I is shown in Figure 5.

Figure 5: Diagram of PWM waveform in Sector I.

Thus, three phase’s duration time of reference voltage can be concluded as

3. Analysis of Neutral-Point Potential Offset and the Balancing Strategy

3.1. Analysis on Neutral-Point Potential Offset of NPC Three-Level Three-Wire APF

As shown in Figure 3, there are 27 switching states and 19 space vectors in the space vector diagram of the NPC three-level converter. These vectors can be divided into four different types, zero vector, small vector, medium vector, and large vector, based on the different influences of neutral-point potential. The detail will be discussed separately in the following.

When zero vector works, such as PPP, the three-phase load is connected to the positive terminal of DC-bus directly. As shown in Figure 6, no current flows into/out of the neutral point O. Therefore, the zero vector does not have any effect on the neutral-point potential.

Figure 6: Zero vector (PPP).

As shown in Figure 7, when the large vector (PNN) works, the three-phase load is connected to the positive and negative terminal of DC-bus, respectively. It can be seen that no current flows into/out of the neutral-point O. So, the large vector does not influence the neutral-point potential, either.

Figure 7: Large vector (PNN).

Figures 8 and 9 show that when the small or medium vector works, the neutral point O is connected to the load. There is some current flowing into/out of the neutral point O, which will affect the neutral-point potential. The small or the medium vector always have the switching state “O,” so there is at least one phase load connected to the neutral point. In such a circumstance, the phase current is equal to the current which flows into/out of the neutral point O. There is the neutral-point potential offset because of the neutral-point current.

Figure 8: Small vector (POO).

Figure 9: Medium vector (PON).

Table 3 shows the neutral-point current corresponding to different vectors. It can be inferred that small vectors appear in pairs, but the two have opposite effects on neutral-point potential. The PWM waveform can be generated by the seven-stage modulation method by combining the original PWM waveform in Figure 5 and the data in Table 3, as shown in Figure 10.

Table 3: Neutral-point current corresponding to different vectors.

Positive small vectors
iNP
Negative small vectors
iNP
Medium vectors
iNP

ONN
ia
POO
−ia
OPN
ia

NON
ib
OPO
−ib
PON
ib

NNO
ic
OOP
−ic
PNO
ic

OPP
ia
NOO
−ia
ONP
ia

POP
ib
ONO
−ib
NOP
ib

PPO
ic
OON
−ic
NPO
ic

Figure 10: Neutral-point current in a switching period.

When the sampling period is small enough, the current of phase current can be considered as constant in a sampling period. According to Figure 10, the average value of neutral-point current iNP can be calculated as

By solving (6), the neutral-point current iNP can be obtained as

3.2. The Neutral-Point Potential Balancing Strategy

In traditional CB-PWM, zero-sequence voltage is injected into three-phase reference voltage to balance the neutral-point potential, which requires complicated calculation. The present study proposes a novel strategy, aiming to make the calculation convenient and simpler.

Compare to the injection of zero-sequence component, we add the common time Terr to three phase’s duration time TX (X = A, B, C) to balance the neutral-point potential offset. After Terr is added, the new three phase’s duration time can be obtained as

Thus, the new neutral-point current is

Based on the principle of charge conservation, the following equation can be obtained:

where Uerr = Udcd − Udcu is the voltage difference between lower and upper DC-link capacitors, Udcu and Udcd the upper and lower DC-link capacitor voltage, respectively, and C = C₁ = C₂ is the capacitance of DC-link. Thus, Terr can be derived from (9) and (10) directly:

Equation (9) shows that Terr can affect the neutral-point current and can adjust the neutral-point potential. When i’NP is positive, the neutral-point potential will decrease. Thus, Terr can be modified by equation (11) to suppress the neutral-point potential offset in theory. The process of modification is shown in Figure 11.

(a)

(b)

Figure 11: Procedure of duration time modification of PWM waveforms. (a) Neutral-point potential to be decreased. (b) Neutral-point potential to be increased.

When is located in the other sectors, Terr can be expressed as follows:

where S is the sector number. Figure 11 shows that the range of common time Terr should follow

4. Experimental Verification

In order to verify the effectiveness of the proposed balancing strategy, experiments for NPC three-level three-wire APF are conducted. The parameters of the experimental platform are listed in Table 4.

Table 4: Parameters of the experimental platform.

Parameters
Value

Phase voltage (Vs)
110 V (RMS)

Frequency of phase voltage
50 Hz

DC-link voltage (2Udc)
400 V

DC-link capacitance (C₁, C₂)
1350 μF

Output inductor (Ls)
4 mH

Switching frequency (fs)
10 kHz

Load resistance (Rd)
30 Ω

Figure 12 shows the photograph of the experiment equipment including AC supply from the grid, nonlinear load, sensor board connected to controller board, and NPC three-level converter board.

Figure 12: Photograph of the experimental platform.

Figure 13 shows some waveforms before and after compensation by APF. The three-phase uncontrolled rectifier bridge connecting serially with a 30 Ω resistor is selected as the typical nonlinear load. The typical load current waveforms can be found from Figure 13(a). Figure 13(b) shows the load current, the grid current after compensation, and the reference current and output current of APF, respectively. The grid current, compared with the distorted load current, is approximately sinusoidal and symmetrical after the compensation. The same conclusion can be drawn after the THD analysis. The THD of load current reaches up to maximum 24.01%. However, the THD of grid-side current sharply falls to 4.5% because of the compensation. Meanwhile, the actual output compensating current is nearly the same as the reference current, suggesting that APF is with good performance. The experiments and analysis above have verified that the three-level three-wire NPC APF has significant positive performance on improving the quality of power grid.

(a)

(b)

Figure 13: Waveforms of some currents. (a) Load current before compensation. (b) Harmonic reference current.

Figure 14 shows the waveforms of upper and lower DC-link voltage. It can be seen that when the neutral-point potential control strategy is not working, the upper and lower voltage Udcu/Udcd diverge in opposite directions. Then, the proposed neutral-point potential scheme starts working. It shows that the differential value between upper and lower DC-link voltage is less than 2 V, suggesting that the neutral-point potential offset is suppressed effectively.

Figure 14: Waveforms of upper and lower DC-link voltage.

The proposed scheme and conventional SVPWM were both programmed on the same TMS320F28335 DSP board to check which algorithm can simplify the calculation. Meanwhile, the same code style and composer configuration were adopted, and all extra optimal measures during the programming were strictly controlled. The results of the experiments showed that it only took DSP 6.4 μs in the proposed scheme to finish the whole calculation, while in conventional SVPWM, it was 9.6 μs, indicating a significant simplification.

5. Conclusions

The present paper, based on a new voltage-second rule for the three-level converter on three-phase three-wire APF systems, proposes a novel simplified neutral-point balancing scheme and verifies its performance in balancing NP potential. Firstly, the duration time of three phases can be calculated directly with this scheme to avoid the complicated selection of space vector sectors by conventional SVPWM. The calculations in the proposed strategy cover multiplication, addition, and few amounts of division. Compared with the large quantity of divisions, even trigonometry operations in conventional SVPWM, the proposed strategy represents a simplified algorithm when applied in the DSP plant.

Secondly, this proposed strategy reconstructs the switching sequence of every phase by modifying the duration time. Its operation is significantly simpler than the traditional method of zero-sequence voltage injection. The experiments in Section 4 have verified the feasibility and effectiveness of the proposed strategy.

Data Availability

The raw/processed data required to reproduce these findings cannot be shared at this time as the data also forms part of an ongoing study.

Conflicts of Interest

The authors declare that there are no conflicts of interest regarding the publication of this paper.

Acknowledgments

This work was supported by the Natural Science Research Project of Jiangsu Higher Education Institutions of China (19KJB470020).

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