Design of an Optimized Asymmetric Multilevel Inverter with Reduced Components Using Newton-Raphson Method and Particle Swarm Optimization

Multilevel inverters have great scope in current developments of grid-connected solar PV systems. Two-level inverters are the simplest kind of multilevel inverter available (MLI). As the number of output levels is raised, the total harmonic distortion decreases. In classic MLI topologies, more electronic components are utilized to get higher-level outputs, which raise the cost, complexity


Introduction
Some common issues arise in the design of medium-voltage converter topologies for a wide range of applications including motor drives, solid-state transformers, and solar photovoltaic systems, including difculties with high-power solar PV systems that make the control circuitry of the inverter more complicated. Te initial development of the multilevel inverter theory was made in 1971 as a replacement for a set of linked power electronic switching devices used in medium-power applications [1]. During the 1971-1981 era, MLIs, such as neutral point clamped (NPC), a fying capacitor (FC), and cascaded H-bridge (CHB), were suggested [2]. Te idea of a three-level NPC converter has acquired popularity as a result of its essential circuit design, and they are still available for purchase on the commercial market today. Te increase in levels of neutral point clamped topology, on the other hand, results in a signifcant increase in the number of clamping diodes [3]. Taking use of the inverse retrieval times of the clamping diode, it is possible to construct an inverter with more levels for medium-power applications using this design [4]. Hence, the neutral point clamped topology and the fying capacitor topologies are too inadequate for medium voltage (MV) and high voltage (HV) applications because they use many condensers requiring prior charging and balancing the capacitors [5,6]. A large DC-link capacitor is required for single-cell design, which restricts its utility to high and medium voltages, notably in solar PV installations, where a large number of PV panels are connected in series [7]. Because a signifcant number of series-connected PV panels have equal maximum power point tracking (MPPT) and series resistance, the overall system efciency will be lowered as a result of the low overall system efciency [8,9]. It is possible to operate MPPT at the module level due to the multicell multilevel CHB converter design, which is adaptable to multiple voltage levels [10]. Furthermore, CHB topologies do not require the use of clamping diodes or capacitors [11,12]. Partial shading and continuous module characteristics will produce mismatch issues [13]. Tese mismatches lead to network imbalance and lower power quality [14]. Utilizing CHB converters for PV applications presents a diferent set of challenges than using them in solid-state transformers or motor drives [15].
Multilevel inverters have made signifcant strides forward in recent times because of their ability to ofer maximum power output at afordable costs [16]. By including the harmonic profle in the IEEE-519 standard, multilevel inverter topologies remove the requirement for massive flters [17]. Electric motors may be guaranteed by lowering THD, dv/dt stress, and common-mode voltages [18]. Multilevel inverters have fewer EMI issues than 2-level and 3-level inverters [19]. Cascading the basic units of the level generation part resulted in a higher output voltage and less THD [20]. Te inverter fnds applications in PV-fed UPS, propulsion systems, PV power integration, and batteryoperated vehicles and needs a simple and direct control method [21]. Terefore, the researchers concentrated on topological construction and modulation [22].
Te new architecture with 5 switches for 7 levels was introduced in an efort to reduce the switches as much as possible and the complexity to improve the cost of building circuits [23]. A new diamond-shaped multilevel inverter was developed in [24] by utilizing switched capacitors and DC voltage sources with dual-mode characteristics. Tis architecture has not redialed any H-bridge back circuit so voltage stress on the switches is lower and can easily be extended to higher levels with fewer switches. A hybrid topology has been proposed by combining 5 levels NPC with 3 levels Ttype converter to generate 7 levels output for induction motor applications [25]. Te architecture uses three foating capacitors per phase, which are balanced during the PWM switching period using switching-state redundancies for each pole voltage level. A back-to-back T-connected hybrid multilevel inverter using the reduced switch confguration that generates an 11-level output has been developed by the authors of [26]. Tis architecture addressed two major drawbacks of traditional MLI topologies such as voltage strain and a larger number of design components. In order to reduce the number of switching components, especially when there are many diferent output voltage levels, a multilevel inverter containing a bidirectional diode has been introduced by the authors of [27]. Tis architecture has fewer semiconductor switches at the same number of output voltage levels than symmetric topologies which have recently and traditionally attempted to reduce the number of switches. Tis makes the proposed inverter a better choice for medium voltage applications such as electric motors and renewable energy systems. Two new topologies have been proposed by the authors of [28] to generate higher levels with a reduced number of switches. Te frst topology utilizes 3 DC sources and 10 switches to generate 15 levels of output. Te second is an extension of the proposed architecture, which uses 4 DC sources and 12 switches to generate 25 levels of output. Structures reported in the literature have addressed several issues such as voltage stress and power losses. However, the use of capacitors in the design of MLIs creates voltage-balancing efects, and the use of diodes will lead to more reverse recovery times. Hence, there is a need to reduce the number of capacitors and diodes in the design of the multilevel inverters.
In this work, an asymmetric MLI with a low switch count was developed, which eliminated the requirement for bidirectional switches, capacitors, and more diodes in the design of the MLI. Due to the absence of bidirectional switches, the proposed topology had no infuence on the reverse recovery times of the diode and voltage-balancing efect of input capacitors, and it makes use of a reduced gate control circuit to accomplish this [29][30][31][32][33]. Te suggested inverter employs a SHEPWM control approach to suppress the lower-order harmonics [34,35]. Te Newton-Raphson (NR) method is a numerical computation method used to optimize the switching angles of the proposed inverter. Also, a swarm-based optimization called particle swarm optimization (PSO) algorithm had been employed on the proposed inverter to optimize the THD of the output. Te suggested inverter operates at three distinct levels (seven levels, eleven levels, and ffteen levels), and the resulting total harmonic distortion has been studied.

Design of Asymmetric Multilevel Inverter
Tis study ofered a simple architecture for an asymmetric inverter suited for varying dc sources, such as SPV systems, in its fndings [20,36]. Figure 1(a) depicts the proposed model's basic cell layout. Te bypass diode is coupled to a single voltage source through a power switch. V dc-out becomes source voltage "V" when switch "S" is switched ON, and when switch "S" is switched OFF, source voltage "V" is separated from load, resulting in "0" for V dc-out .
To construct the inverter's "n" cell structure, which is also referred to as the level generation part (primary circuit), basic cells are cascaded as illustrated in Figure 1(b). A multilevel output can only be generated with a positive bias in this "n" cell setup. Figure 1(c) shows a full-bridge inverter for the polarity generation part (auxiliary circuit). Te proposed inverter was structured by the back-to-back interconnection of the level generation part and polarity generation part. Tus, a complete output cycle of positive 2 Mathematical Problems in Engineering and negative polarity can be achieved by combining the primary and auxiliary circuits together. A polarity generator is similar to the H-bridge module and is used to generate 15 diferent output voltage levels, seven of which are positive, seven of which are negative, and one of which is zero. Figure 2 depicts the structure of the proposed multilevel inverter with a 15-level output. Tis topology includes three dc sources, seven switches, and three diodes. Because of the suggested inverter and switching sequence selections, it is unlikely for IGBTs or diodes to die short circuits with the dc sources. Te rating of a signifcant number of dc sources is determined by the magnitude of their output levels. Te V dc step voltage at the output is specifed by the dc source reduced voltage rating. Table 1 shows a variety of potential dc voltage source combinations.
Te binary technique is one of the three options for dc source selection that are being evaluated for this investigation because multilevel inverters operate at great efciency while experiencing minimal power losses and increased output voltage levels with the smallest number of devices. As a result, the following dc sources are recommended for 15-level output: As an added beneft, this technique ofers asymmetrical operation to multilevel inverters, which is perfect for varying PV voltages caused by changing solar irradiation. For various output step voltages ranging from +7 V dc to −7 V dc , including the "0" voltage level, the switching sequence is variable.
Te auxiliary circuit switches S 4 and S 5 conduct for 7 levels of a +ve half cycle, whereas switches S 6 and S 7 conduct for 7 levels of a −ve half cycle. Short-circuiting the load with switches S 4 & S 6 on, or S 5 & S 7 on, yields the "0" output level. By operating the main and auxiliary circuits as per the switching paths indicated in Table 2, the proposed converter produces a ffteen-level output voltage.
Te ON-OFF switching states of all seven switches and diferent operating modes of the proposed 15-level inverter are shown in Figure 3

Comparative Analysis with Conventional Inverters
Te core objective of a reduced switch multilevel inverter is to increase the number of levels while employing a few electronic components. Consequently, several contrasts were established among the suggested topology and other multilevel inverters of a similar kind, including switch count, the number of diodes, and dc sources.     Figure 4(a) provides a comparative analysis of the number of switches, sources, diodes, and capacitors required for various confgurations referenced in this paper and the suggested topology. Tis contrast illustrates that the proposed topology is designed with fewer components. Different components required with respect to the number of levels are presented in Figure 4(b). Figure 5 shows the comparison between the number of switches, diodes, dc sources, and total standing voltages (TSV) of the proposed inverter with other topologies. Here, the comparisons were made with the recent topologies reported in the literature for analyzing the efectiveness of the proposed topology. From these comparisons, it is evident that the proposed topology utilizes less number of components than all other topologies.

Fundamental Switching Frequency Control (SHEPWM)
Multilevel inverters beneft from selective harmonic elimination, which is one of the most efective PWM control     techniques available. Selective harmonic elimination pulse width modulation (SHEPWM) can be used to accomplish FSFC control. In most cases, the waveform of the output of an inverter is stated using the Fourier series expansion. In equation (2), the simplifed expression of inverter output is represented in the following equation: where V n � n th harmonic and the quarter-odd wave's symmetry makes the even harmonics zero. So V n is given in equation (3) neglecting the even-order harmonics cos nα i ; for odd values of'n'0; for even values of'n' where α i is the switching angles of i th harmonic and is between 0 0 -90°(i.e., 0 < α i < π/2). SHEPWM suppresses lower-order harmonics while harmonic flters eliminate the rest. Te 5 th , 7 th , 11 th , 13 th , 17 th , and 19 th harmonic voltages were suppressed using a 15-level asymmetric inverter using SHEPWM control. Using 15-level output reduces bulky and costly flters by reducing the 5 th to 19 th harmonics. Equation (4) can be found by extending equation (3) where 19 are the harmonic voltages of 5 th , 7 th , 11 th , 13 th , 17 th , and 19 th harmonics, respectively, and as a consequence, they are equal to zero, and the resultant could be given in equation (6). Te 1 st harmonic in equation (4) is equal to the modulation index, which may be represented as follows: where V 1 max � Peak fundamental voltage � V 1 max � 4kV dc /π, V 1 � Actual funda mental voltage, k � Degree of freedo m � (N − 1)/2, N � No of levels
Te output harmonic voltages are infuenced by the switching angles of the inverter. When attempting to meet the aforementioned goals, the generalized harmonic voltage objective function (OF) takes on the following form: To minimize the 5 th , 7 th , 11 th , 13 th , 17 th , and 19 th harmonics, equation (8) could be expanded as follows: Te purpose of this study is to lower the total harmonic distortion (THD) by minimising the aforementioned objective function. Te transcendental equation (6), which fulfl the constraint of equation (7) with the objective function (9), could be solved by utilizing the N-R technique for the proposed multilevel inverter to achieve the lowest total harmonic distortion (THD) and the best switching angles.

Results and Discussions
Seven IGBT switches, three switched diodes, and three DC sources are used to construct the suggested asymmetric inverter, which is implemented in MATLAB-Simulink. To produce the switching pulses, a pulse width modulation technique known as selective harmonic elimination has been used. Among other characteristics, the switching frequency is 50 Hz, the maximum harmonic frequency is 1 kHz, and the Nyquist frequency for total harmonic distortion is 5 kHz. Te inverter's load is modeled as a nonresistive load with R � 27 Ω and L � 10 mH. Te nonlinear equations described in equation (6) have been solved by using the Newton-Raphson method and the particle swarm optimization 8 Mathematical Problems in Engineering method for getting the switching angles of the proposed inverter. Te switching angles are evaluated using SHEPWM at diferent modulation indexes, and the best THD is obtained at a 0.9 modulation index.

Computation of Switching Angles and Analysis of Results
Using Newton-Raphson Method. Te seven switching angles for seven switches in the inverter are frst computed by a numerical successive approximation technique known as Newton-Raphson (N-R) approach [33]. Te computation of switching angles involves equations (6) with (7). Te step-by-step procedure followed in the N-R method for the solution of nonlinear equations is described as follows: Step 1: For the calculation of switching angles, a matrix is formulated with seven (1-7) switching angles in equation (10) as follows: Step 2: Te nonlinear system matrix is formulated in equation (11), and the transpose matrix of its partial derivation concerning switching angles is given in equation (12) F i � Step 3: Formulation of harmonic magnitude matrix represented in the following equation: Equations (3.5) and (3.12) are modifed and rewritten as Te matrices (10)- (14) are simulated in MATLAB software for the programmed N-R method, which is implemented as described in the following steps: Step 1: Predict the initial switching angles using the equal area criterion with the following equation: Step : Tis step involves the design equations of the N-R approach from the following equations (16) to (19) Equation (14) is linearized to get the α 0 and Equation (18) can be solved using the inverse of the equation represented in the following form: Mathematical Problems in Engineering Step 3: Update the initial values using the following equation: Steps 2 & 3 are repeated till the dα i is satisfed for the degree of accuracy, and to satisfy the constraints, α 1 < α 2 < α 3 < α 4 < α 5 < α 6 < α 7 < π/2. Tus, the switching angles α 1 to α 7 are evaluated using the Newton-Raphson approach, and the same is stored in the lookup tables for diferent modulation indexes. Tese switching angles are retrieved from the memory of lookup tables during the realtime operation of the inverter for the required modulation index. Te proposed inverter was operated at diferent levels with the variation in choice of dc source as described as follows.

Equal Magnitude of dc Sources.
Considering the input dc sources as the ratio of 1 : 1 : 1, i.e., all the dc sources with equal magnitude, a seven-level output voltage is produced at the inverter output. Te magnitudes of the dc sources are assumed as V 1 � 37 V, V 2 � 37 V, and V 3 � 37 V, resulting in a peak voltage of 111 V. Figure 6 depicts the switching pulses generated by the proposed inverter's seven-level operation. Figure 7 depicts the 7-level output voltage waveform of the proposed inverter with equal magnitude dc sources, and Figure 8 depicts the corresponding THD of the 7-level output of the proposed inverter, which is 15.36%.

Unequal Magnitude of dc Sources.
Considering the input dc sources as the ratio of 1 : 2 : 2, i.e., the dc sources with unequal magnitude, an eleven-level output voltage is produced at the inverter output. Here, the magnitude of dc sources is taken as V 1 � 37 V, V 2 � 74 V, and V 3 � 74 V to get a peak voltage of 185 V. Te switching pulses of the elevenlevel operation of the proposed inverter are shown in Figure 9. Figure 10 shows the 11-level output voltage waveform of the proposed inverter with an unequal magnitude of dc sources. Figure 11 shows the corresponding THD of the 11level output of the proposed inverter, which is 11.17%.

Binary Approach of DC Sources.
Considering the input dc sources as the ratio of 1 : 2 : 4, i.e., the dc source magnitudes are diferent from one to another, a ffteen-level output voltage is produced at the inverter output. Here, the magnitude of dc sources is taken as V 1 � 37 V, V 2 � 74 V, and V 3 � 148 V to get a peak voltage of 259 V. Te switching angles were computed for diferent modulation indices from 0.5 to 1 Newton-Raphson method and tabulated in Table 3. Te corresponding THD of output voltage for all of these modulation indexes is also calculated and found to be the minimum (7.3%) at 0.9 modulation index.
Te switching pulses corresponding to the generated switching angles are shown in Figure 12(a) for the primary circuit and Figure 12(b) for an auxiliary circuit. Figure 13 shows the 15-level output voltage waveform of the proposed inverter with the binary approach of dc sources (1 : 2 : 4 ratio), Figure 14 shows the load current waveform for 15level operation, and Figure 15 shows the corresponding THD of the 15-level output of the proposed inverter, which is 7.3%. Figure 14 confrms that the output current waveform approximately resembles the sinusoidal waveform without using any flter at the output of the inverter. Also, it is in phase with the load voltage so that the power factor is maintained approximately unity.

Computation of Switching Angles and Analysis of Results
Using Particle Swarm Optimization. PSO is defning swarms' sociological behavior. Each particle's PSO vectors are 1 × N and the vector of each particle. Te best individual location in an identifed particle is the local best, and the best position in the whole swarm is the global best. PSO is ideally suited to solving complex problems due to its low computation efort and quick computer coding. Initial values such as other traditional iterative methods are not required for PSO. In the following steps, the PSO mechanism is articulated: Step 1: Initialize the parameters of particle vectors X i , V i , P best , G best , and inertia weight of the particle C 0 . Choose the number of generations as 200 and the size of the population as 50, and every particle is randomly initialized as switching angles between 0°and 90°.
Step : Test the conditions for (C 1 + C 2 )/2 < C 0 < 1. Te system would then be guaranteed to converge to a stable equilibrium if the two criteria were met. If false, go to Step 1.
Step 3: Te new position and velocity vectors of particles were determined using the following equation: Ten, the new position is defned as follows: Step 4: Evaluate the objective function of the particles using equation (23) to fnd the switching angles (1 to 7), such that the harmonics of the 5 th , 7 th , 11 th , 13 th , 17 th , and 19 th harmonics are eliminated at the inverter output.
Step 5: Check for the constraint of the objective function as            Step 6: Check for P(X i ) < P(P i ), if not then i = i + 1 go to step 3.
Step 7: Update the particle's best local position if the best local position is better than before. Tus, replaces the local best position.
Step 9: Termination criteria for a maximum of 200 iterations and terminate the process if the optimal switching angles are achieved. Figure 16 illustrates the control methodology for the proposed inverter. Here, the inverter is controlled by optimal switching angles. Te optimal switching angles of the MLI are obtained by synthesizing the inverter's output into Fourier series representation, as shown in equation (3). Tis equation is further expanded in terms of the switching angles of the inverter as given in equation (4). Additionally, the nonlinear transcendental equations were formulated by considering the harmonics to be minimized, as shown in equation (6).
Using Simulink's solver, the particle swarm optimization (PSO) is used to fnd the best possible switching angles based on the objective function given in equation (9). Te fundamental output voltage equation is assigned with modulation index, which is obtained from the dc-link control. Te solutions of the nonlinear equations are stored in lookup tables. Ten, the switching angles decoder decodes the fring angles of the corresponding switch and produces the pulse related to the corresponding switching angle.
Te switching angles for each modulation index are computed ofine and stored in lookup tables. Te switching angles for the modulation index from 0.5 to 1 were determined using the PSO algorithm and tabulated in Table 4. Te corresponding THD of output voltage for all of these modulation indexes is calculated and found to be the minimum (4.23%) at 0.9 modulation index. Te PSO takes 114 iterations to converge      Figure 17.
Te switching pulses corresponding to the generated switching angles are shown in Figure 18(a) for the primary circuit and Figure 18(b) for an auxiliary circuit. Figure 19 shows the 15-level output voltage and current waveforms of the proposed inverter with the binary approach of dc sources (1 : 2 : 4 ratio), and Figure 20 shows the corresponding THD of the 15-level output of the proposed inverter, which is 4.23%. Figure 19 confrms that the output current waveform approximately resembles the sinusoidal waveform without using any flter at the output of the inverter. Also, it is in phase with the load voltage so that the power factor is maintained approximately unity.
Te total harmonic distortion (THD) of the 15-level inverter output is measured using switching angles calculated by the PSO method at a modulation index of 0.9. Te output voltage's total harmonic distortion (THD) is 4.23% at 264.9 V, as shown in Figure 20. Te THD of the results of the proposed inverter was compared with the work reported in the literature and is given in Table 5. Te detailed comparison of the results of the proposed inverter was compared with the work reported in the literature. It reveals that the proposed asymmetric inverter utilizes less number of switches compared to the other topologies and also produces less % THD without employing any flter at the output.

Conclusion
An asymmetric 15-level inverter with 7 switches and 3 diodes had been developed in this paper to optimize the size of the design topology. Te inverter also operated 7-level and 11-level operations with a proper choice of dc source selection. Te lower-order dominant harmonics in the inverter output had been minimized using a low-frequency switching modulation (SHEPWM). Te transcendental equations generated in SHEPWM had been solved using the Newton-Raphson method and particle swarm optimization methods to obtain the switching angles. Te THD of the inverter output had been analyzed for 7-level, 11-level, and 15-level operations using equal magnitude, unequal magnitude, and binary approaches of dc sources, respectively. Using the NR method, the THD obtained at output voltage for 7-level operation is 15.36%, for 11-level operation is 11.17%, and for 15-level operation is 7.30%. Hence, it is confrmed that the 15-level operation of the proposed inverter produces lower THD than other level operations. Consequently, the proposed inverter is controlled by using particle swarm optimization for 15-level operation with the binary choice of the sources, and the THD obtained at output voltage is 4.23%. Tese results are compared with the similar topologies presented in the literature and concluded that the proposed inverter gives lower THD using the PSO algorithm.

Data Availability
Te data sources employed for analysis are presented in the text.

Conflicts of Interest
Te authors declare that they have no conficts of interest.