A low-noise phase modulator, using finite-impulse-response (FIR) filtering embedded delta-sigma (ΔΣ) fractional-N phase-locked loop (PLL), is fabricated in 0.18

Polar transmitters can achieve both high power efficiency and good linearity and become growing popular in modern wireless systems [

The delta-sigma (

Polar transmitters with

The quantization noise qn of the DSM needs be concerned for a PLL. The existing noise cancellation technique [

In this paper, with simplified inverse-FIR and -PLL digital filters proposed to compensate for the signal attenuation, an FIR-embedded

The paper is organized as follows. Section

Figure

Conceptual diagram and signal model of FIR-embedded

Under PLL reference clock

The signal path from the DSM input to the voltage-controlled oscillator (VCO) output, excluding the FIR filtering, is functionally equivalent to a DAC with a PLL TF

Figure

Proposed low-noise

Considering the PLL inherently contains a multiplication factor of

A 4th-order type-II fractional-N PLL with FIR-embedded

Figure ^{21}−1 pseudo random bit source (PRBS) with a normal burst frame architecture produces the transmit data. The symbol rotation operation with

Block diagram of baseband

The modified CORDIC [

For the given five consecutive phase component inputs, a derivation algorithm using a five-point-interpolation method with phase jump preprocess is shown in (

Figure

Simulated envelope and frequency components for EDGE signal.

Since the fractional-N PLL has a low-passed feature with additional FIR attenuation, digital compensation filters need to be designed not only to compensate for the limited path bandwidth caused by the PLL but also to offset the gain attenuation due to the FIR filtering:

Larger FIR parameter

Simulated frequency responses of FIR-compensated filters: ideal versus proposed implementations.

Since the type-II PLL with 4th-order TF inherently has 4 poles and 1 zero in

Simulated frequency response of presented phase modulator.

To ensure phase-modulation linearity, it is important to ensure strict match of the TFs between the inverse-

With embedded FIR filtering, the 4th-order type-II PLL with 100-kHz bandwidth employs eight PFDs in parallel, and all the lead-lag phase errors converted to push-pull pulse currents are summed at the output of the 8-phase charge pump. The schematic of the 8-phase charge pump is shown in Figure

Multiphase charge pump schematic.

The summed push-pull error current is low-passed filtered to generate an error control voltage

LC VCO schematic.

The VCO differential output is sent to the sequent MMD and compared to the reference clock. Figure

PS-based MMD module.

CML divider-by-2 schematic.

Considering that fewer DSM output levels result in smaller instantaneous phase error at the PFD output and thus less phase noise, and on the other hand, the wider DSM output levels have more efficient randomization and dithering and generate less fractional spurs to the PLL [

The proposed digital compensation filters and FIR-embedded fractional-N PLL are fabricated in 0.18 ^{2} and the measured power dissipation of 20 mW from a 1.6 V supply, excluding the class-E PA. In order to save chip pads, on-chip 4-bit series-to-parallel conversion (S4P) and off-chip 4-bit parallel-to-series conversion (P4S) are used to accomplish the data communication between the chip and FPGA.

Chip micrograph.

The simulated and measured phase noise depicted in Figure

Measured phase noise of fractional-N PLL.

Figure

Simulated modulation performance of proposed architecture for 8PSK.

Figure

Transmitter output constellation for GMSK.

A phase modulator employing FIR-compensated

The author declares that there is no conflict of interests regarding the publication of this paper.

The author would like to thank the National Natural Science Foundation of China (no. 61306037) for the financial support.