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Unreliable message storage severely degrades the performance of LDPC decoders. This paper discusses the impacts of message errors on LDPC decoders and schemes improving the robustness. Firstly, we develop a discrete density evolution analysis for faulty LDPC decoders, which indicates that protecting the sign bits of messages is effective enough for finite-precision LDPC decoders. Secondly, we analyze the effects of quantization precision loss for static sign bit protection and propose an embedded dynamic coding scheme by adaptively employing the least significant bits (LSBs) to protect the sign bits. Thirdly, we give a construction of Hamming product code for the adaptive coding and present low complexity decoding algorithms. Theoretic analysis indicates that the proposed scheme outperforms traditional triple modular redundancy (TMR) scheme in decoding both threshold and residual errors, while Monte Carlo simulations show that the performance loss is less than 0.2 dB when the storage error probability varies from

Low-Density Parity-Check (LDPC) codes are widely used in space communications due to their capacity-approaching capabilities [

There are studies on the effects of unreliable hardware on LDPC decoders. Varshney considered the thresholds and residual errors of LDPC codes with the faulty Gallager A decoding in the earlier stage [

In general, the existing works treated each finite-precision message as an integer, while this paper discusses the various impacts of different bits of the finite-precision message. We develop a discrete density evolution analysis for LDPC decoders with faulty messages. It indicates that the sign bits of the messages play the most important role in the decoding performance of LDPC codes, which means setting protection on sign bits is efficient enough. To protect the sign bit inside each quantized message, the traditional method is the static triple modular redundancy (TMR) scheme as applied in [

Based on the aforementioned observations, we propose an adaptive embedded coding scheme for the unreliable messages to achieve a robust LDPC decoder. First, we put the messages into packages by taking advantage of the parallel message architecture of the quasi-cyclic (QC) LDPC decoders. The structure of message package permits more efficient block coding schemes for the sign bits other than simple TMR method. Then, two LSBs are adaptively employed for sign bits protection based on the magnitude level of message package. Moreover, we introduce a construction of Hamming product code for the adaptive coding, which has a multistage coding structure and outstanding error-correcting capability. We also discuss low complexity iterative decoding algorithms for the Hamming product code. Both theoretical analysis and Monte Carlo simulations demonstrate that the proposed adaptive message coding scheme outperforms the TMR scheme in decoding both thresholds and residual errors for various storage error levels.

The paper is organized as follows. In Section

The hardware architecture of the QC-LDPC decoder is shown in Figure

The partially parallel architecture of LDPC decoders.

For the existing studies on LDPC decoders with faulty hardware, there are several widely accepted error models. As shown in Figure

Existing faulty storage models.

However, these two error models still have limitations for practical LDPC decoders. For example, the BSC error model is mostly utilized in bit flipping decoding algorithms, such as Gallager A decoding and Gallager B decoding, which make more sense in theoretical analysis. The AWGN error model is adopted in infinite-precision soft-decoding algorithms, where the messages are in continuous domain and assumed to be added with Gaussian noise by the faulty hardware.

In this paper, we consider the practical LDPC decoders, where finite-precision decoding algorithm is utilized. Following the studies in [

The quantized BSC model for the unreliable memories.

In this section, we define a discrete density evolution method for the analysis of finite-precision BP decoding of LDPC codes, which will give the performance of decoding thresholds and residual error ratios for LDPC decoders with different message protection schemes.

It has been proved by Varshney [

In the density evolution analysis, we define

Since the codewords are assumed to be all zero sequences, to initialize the discrete density evolution,

After the initialization, the density evolution executes its iterations. Firstly, in the VNU nodes,

Secondly, in the CNU nodes, the magnitude values of messages are mapped into log-domain by function

Finally, after the maximum iterations, the decoding decision is made in the VNU nodes, where the PMF is calculated as

Above is the conventional discrete density evolution method for finite-precision LDPC decoders. However, this paper considers the issue of message storage errors, which means each message will suffer transformation of PMF outside the nodes. In the following, we will model the PMF transformation of unreliable message in density evolution.

Define

Based on the discrete density evolution method defined in Section

We execute the discrete density evolution on a

The thresholds of protecting various message bits.

For LDPC decoders, the cost is overwhelming to protect every message bit. However, as mentioned before, it is not necessary since the sign bits are demonstrated to be the most important. Thus, following the idea of unequal error protection [

As in [

Performance analysis under different storage error ratios.

From the analysis, it can be observed that when the storage error ratio is high (e.g.,

We noticed that a similar adaptive coding scheme for approximate computing with faulty storage has been proposed in [

The aforementioned scheme makes full use of the LSBs in the messages. It has efficiently protected the unreliable messages without using any storage redundancy. However, there are some disadvantages for this protection scheme. Firstly, the adaptive coding is executed inside the single message, which is typically quantized with no more than 7 bits for the reason of complexity [

We demonstrate the exact error-correcting performance of the sign bits for this coding scheme as follows. In the first case where the MSB is 1, the encoding will be executed. If the MSB is read correctly, the

In this section, we firstly present the architecture of the proposed adaptive coding scheme. Then, a specific construction of Hamming product code for the adaptive strategy is provided. Next, we analyze the performance of the proposed scheme theoretically.

As analyzed in Section

What is more, existing studies execute protection on each single message, where only simple coding scheme (such as TMR) can be utilized. However, we notice that LDPC decoders are usually implemented with a partially parallel architecture, as described in Section

As shown in Figure

If

If

If

Structure of adaptive package coding.

Reversibly, when the messages are read from RAMs, adaptive decoding is executed based on the value of

In this section, we will give a specific code construction for the adaptive coding scheme.

To adaptively protect the sign bits of message packages, the ideal block code should have the features of multistage coding structure, as well as low coding complexity and appropriate block length. We introduce Hamming product codes as the adaptive package codes based on the following advantages. First, the product codes are constructed by several subcodes, whose coding process can be easily designed into multistage. Second, Hamming codes have the simplest decoders and encoders among all of the block codes, which only consist of several basic logic gates. Moreover, as the data is usually operated in bytes, where each byte contains 8 bits, in order to make the package codes suitable for the data operations, we choose the modified Hamming product code, which is

As shown in Figure

The

In this section, we will also utilize the discrete density evolution method to analyze our proposed adaptive package coding scheme. As mentioned before, we should deduce the error vector

As defined in Section

We set

Performance analysis on adaptive package coding scheme with

Performance analysis on adaptive package coding scheme with

The Hamming product code we have introduced has an outstanding minimum distance characteristic. However, its error-correcting capability can only be achieved under the maximum likelihood (ML) decoding, which has high complexity and is not practical for LDPC message protection. In this section, we will discuss specific decoding algorithms for the Hamming product code, which achieves good performance with low complexity.

For the subcode

Iterative step: the row subcodes and the column subcodes execute their decoding algorithms iteratively. During the decoding, if the Hamming decoder cannot locate the error bits, keep the block unchanged; otherwise, update the block. After several iterations (we set it to 2 iterations here), stop the iterative decoding.

Decision step: firstly, the error detecting is executed by the Hamming decoders. Define

We utilize a low-order approximation method to evaluate the performance of the Hamming product code with the proposed decoding algorithm. Since two states are defined for the output bits, we use two parameters to describe the decoding performance: the bit erasure ratio

Low-order error pattern analysis.

Error pattern order | Bit erasures total | Bit errors total |
---|---|---|

1 | 0 | 0 |

2 | 0 | 0 |

3 | 256 | 16 |

4 | 13008 | 1680 |

The low-order approximation of

In fact, the performance of Hamming product code can be further improved at the expense of complexity for the iterative decoding. In this section, an enhanced decoding scheme is proposed to obtain better performance by introducing more decision logics.

As analyzed in Section

The 3rd-order error patterns.

Error pattern

Erasure pattern

As a matter of fact, the decoding erasure bits and error bits caused by the 3rd-order error patterns all occurred in the similar ways mentioned above. Based on this analysis, an enhanced decoding scheme is proposed by adding the following two decision logics in the decision step:

3rd-order error bit decision: after the error detecting, if the index sets

3rd-order erasure bit decision: if one bit is decoded into different values by the row subcode and the column subcode, it is declared as an erasure bit.

The performance of the enhanced decoding scheme is shown in Figure

The performance of the enhanced decoding scheme.

Another key issue is the complexity of decoding Hamming product code compared with traditional TMR scheme. As TMR only consumes a majority decision logic module to decode the duplicate check, it is generally believed that introducing advanced long block codes will definitely increase the hardware complexity. However, in this section, based on the Field Programmable Gate Array (FPGA) implementation, we will see that the hardware complexity of Hamming product code can be even lower than TMR scheme in some cases. Moreover, there will be a flexible tradeoff between hardware consumption and decoding delay for the Hamming product code.

In applications, LDPC encoder and decoder are mostly implemented based on FPGA, which is reconfigurable and widely adopted in communication systems. A major difference between FPGA and the Application Specific Integrated Circuit (ASIC) is the structure of combinational logic circuit. For FPGA, the combinational logic is not composed of actual logic gates. Instead, it is based on a structure called Lookup Table (LUT), which is actually a small block of RAM. The input of combinational logic is connected to the RAM’s address, and the logical output is presynthesized and stored into the RAM. Thus arbitrary logical operation can be implemented by looking up into the storage for each input logic combination. For conventional FPGA, 4-input and 6-input LUTs are mostly equipped. As a result, the TMR decision is actually processed by a 4-input LUT on FPGA. Next, we will compare the consumption of LUTs for the TMR and proposed schemes. In our proposed adaptive message coding scheme, each 16 messages are grouped into one package. Consequently, the corresponding consumption for TMR scheme is 16 4-input LUTs totally. Comparatively, the consumption of the proposed scheme is shown in Figure

Tradeoff between complexity and decoding delay.

Serial number | Consumption of LUTs | Decoding clocks |
---|---|---|

1 | 4 inputs | 8 |

2 | 4 inputs | 4 |

3 | 4 inputs | 2 |

The implementation structure of various schemes based on LUT.

In this section, Monte Carlo simulations are executed on the finite length codewords of LDPC. We utilize the

Simulations on the

This paper considered the challenge of implementing LDPC decoders on unreliable memories. We explored the effects of various message bits on finite-precision LDPC decoders and introduced an effective adaptive coding scheme based on the magnitude level of messages. We put the messages into packages and proposed a Hamming product code to adaptively correct the sign bits, as well as discussing two low complexity decoding algorithms. The discrete density evolution analysis showed that the proposed scheme outperforms traditional TMR scheme in decoding both threshold and residual errors under various storage error levels. Moreover, Monte Carlo simulations showed that the proposed scheme could at least obtain a gain of 0.3 dB to the static TMR scheme when the storage error probability was from

The authors declare that they have no conflicts of interest.

This work was supported by the National Natural Science Foundation of China (NSFC 91538203), the new strategic industries development projects of Shenzhen City (JCYJ20150403155812833), and the Beijing Innovation Center for Future Chips, Tsinghua University.